FabGL
ESP32 Display Controller and Graphics Library
Z80.cpp
1/*
2 Z80 emulator code derived from Lin Ke-Fong source. Copyright says:
3
4 Copyright (c) 2016, 2017 Lin Ke-Fong
5
6 This code is free, do whatever you want with it.
7
8 2020 adapted by Fabrizio Di Vittorio for fabgl ESP32 library
9 */
10
11
12
13#include "Z80.h"
14
15
16#pragma GCC optimize ("O2")
17
18
19namespace fabgl {
20
21
22/* Write the following macros for memory access and input/output on the Z80.
23 *
24 * Z80_FETCH_BYTE() and Z80_FETCH_WORD() are used by the emulator to read the
25 * code (opcode, constants, displacement, etc). The upper 16-bit of the address
26 * parameters is undefined and must be reset to zero before actually reading
27 * memory (use & 0xffff). The value x read, must be an unsigned 8-bit or 16-bit
28 * value in the endianness of the host processor.
29 *
30 * Z80_READ_BYTE(), Z80_WRITE_BYTE(), Z80_READ_WORD(), and Z80_WRITE_WORD()
31 * are used for general memory access. They obey the same rules as the code
32 * reading macros. The upper bits of the value x to write may be non-zero.
33 * Z80_READ_WORD_INTERRUPT() and Z80_WRITE_WORD_INTERRUPT() are same as
34 * respectively Z80_READ_WORD() and Z80_WRITE_WORD(), except they are only used
35 * for interrupt generation.
36 *
37 * Z80_INPUT_BYTE() and Z80_OUTPUT_BYTE() are for input and output. The upper
38 * bits of the port number to read or write are always zero. The input byte x
39 * must be an unsigned 8-bit value. The value x to write is an unsigned 8-bit
40 * with its upper bits zeroed.
41 *
42 * All macros have access to the following three variables:
43 *
44 * state Pointer to the current Z80_STATE. Because the
45 * instruction is currently executing, its members may not
46 * be fully up to date, depending on when the macro is
47 * called in the process. It is rather suggested to access
48 * the state only when the emulator is stopped.
49 *
50 * elapsed_cycles Number of cycles emulated. If needed, you may add wait
51 * states to it for slow memory accesses. Because the
52 * macros are called during the execution of the current
53 * instruction, this number is only precise up to the
54 * previous one.
55 *
56 *
57 * Except for Z80_READ_WORD_INTERRUPT and Z80_WRITE_WORD_INTERRUPT, all macros
58 * also have access to:
59 *
60 *
61 * registers Current register decoding table, use it to determine if
62 * the current instruction is prefixed. It points on:
63 *
64 * state.dd_register_table for 0xdd prefixes;
65 * state.fd_register_table for 0xfd prefixes;
66 * state.register_table otherwise.
67 *
68 * pc Current PC register (upper bits are undefined), points
69 * on the opcode, the displacement or constant to read for
70 * Z80_FETCH_BYTE() and Z80_FETCH_WORD(), or on the next
71 * instruction otherwise.
72 *
73 * Except for Z80_FETCH_BYTE(), Z80_FETCH_WORD(), Z80_READ_WORD_INTERRUPT, and
74 * Z80_WRITE_WORD_INTERRUPT, all other macros can know which instruction is
75 * currently executing:
76 *
77 * opcode Opcode of the currently executing instruction.
78 *
79 * instruction Type of the currently executing instruction, see
80 * instructions.h for a list.
81 */
82
83/* Here are macros for emulating zexdoc and zexall. Read/write memory macros
84 * are written for a linear 64k RAM. Input/output port macros are used as
85 * "traps" to simulate system calls.
86 */
87
88
89#define Z80_READ_BYTE(address, x) \
90{ \
91 (x) = (m_readByte(m_context, (address) & 0xffff)); \
92}
93
94#define Z80_FETCH_BYTE(address, x) Z80_READ_BYTE((address), (x))
95
96#define Z80_READ_WORD(address, x) \
97{ \
98 (x) = (m_readByte(m_context, (address) & 0xffff) | (m_readByte(m_context, ((address) + 1) & 0xffff) << 8)); \
99}
100
101#define Z80_FETCH_WORD(address, x) Z80_READ_WORD((address), (x))
102
103#define Z80_WRITE_BYTE(address, x) \
104{ \
105 m_writeByte(m_context, (address) & 0xffff, (x)); \
106}
107
108#define Z80_WRITE_WORD(address, x) \
109{ \
110 m_writeByte(m_context, (address) & 0xffff, (x)); \
111 m_writeByte(m_context, ((address) + 1) & 0xffff, (x) >> 8); \
112}
113
114#define Z80_READ_WORD_INTERRUPT(address, x) Z80_READ_WORD((address), (x))
115
116#define Z80_WRITE_WORD_INTERRUPT(address, x) Z80_WRITE_WORD((address), (x))
117
118#define Z80_INPUT_BYTE(port, x) \
119{ \
120 (x) = m_readIO(m_context, (port)); \
121}
122
123#define Z80_OUTPUT_BYTE(port, x) \
124{ \
125 m_writeIO(m_context, (port), (x)); \
126}
127
128
129
130
131
132
133/* Some "instructions" handle two opcodes hence they need their encodings to
134 * be able to distinguish them.
135 */
136
137#define OPCODE_LD_A_I 0x57
138#define OPCODE_LD_I_A 0x47
139
140#define OPCODE_LDI 0xa0
141#define OPCODE_LDIR 0xb0
142#define OPCODE_CPI 0xa1
143#define OPCODE_CPIR 0xb1
144
145#define OPCODE_RLD 0x6f
146
147#if defined(Z80_CATCH_RETI) && defined(Z80_CATCH_RETN)
148# define OPCODE_RETI 0x4d
149#endif
150
151#define OPCODE_INI 0xa2
152#define OPCODE_INIR 0xb2
153#define OPCODE_OUTI 0xa3
154#define OPCODE_OTIR 0xb3
155
156
157
158/* Instruction numbers, opcodes are converted to these numbers using tables
159 * generated by maketables.c.
160 */
161
162enum {
163
164 /* 8-bit load group. */
165
166 LD_R_R,
167 LD_R_N,
168
169 LD_R_INDIRECT_HL,
170 LD_INDIRECT_HL_R,
171 LD_INDIRECT_HL_N,
172
173 LD_A_INDIRECT_BC,
174 LD_A_INDIRECT_DE,
175 LD_A_INDIRECT_NN,
176 LD_INDIRECT_BC_A,
177 LD_INDIRECT_DE_A,
178 LD_INDIRECT_NN_A,
179
180 LD_A_I_LD_A_R, /* Handle "LD A, I" and "LD A, R". */
181 LD_I_A_LD_R_A, /* Handle "LD I, A" and "LD I, A". */
182
183 /* 16-bit load group. */
184
185 LD_RR_NN,
186
187 LD_HL_INDIRECT_NN,
188 LD_RR_INDIRECT_NN,
189 LD_INDIRECT_NN_HL,
190 LD_INDIRECT_NN_RR,
191
192 LD_SP_HL,
193
194 PUSH_SS,
195 POP_SS,
196
197 /* Exchange, block transfer, and search group. */
198
199 EX_DE_HL,
200 EX_AF_AF_PRIME,
201 EXX,
202 EX_INDIRECT_SP_HL,
203
204 LDI_LDD, /* Handle "LDI" and "LDD". */
205 LDIR_LDDR, /* Handle "LDIR" and "LDDR". */
206
207 CPI_CPD, /* Handle "CPI" and "CPD". */
208 CPIR_CPDR, /* Handle "CPIR" and "CPDR". */
209
210 /* 8-bit arithmetic and logical group. */
211
212 ADD_R,
213 ADD_N,
214 ADD_INDIRECT_HL,
215
216 ADC_R,
217 ADC_N,
218 ADC_INDIRECT_HL,
219
220 SUB_R,
221 SUB_N,
222 SUB_INDIRECT_HL,
223
224 SBC_R,
225 SBC_N,
226 SBC_INDIRECT_HL,
227
228 AND_R,
229 AND_N,
230 AND_INDIRECT_HL,
231
232 XOR_R,
233 XOR_N,
234 XOR_INDIRECT_HL,
235
236 OR_R,
237 OR_N,
238 OR_INDIRECT_HL,
239
240 CP_R,
241 CP_N,
242 CP_INDIRECT_HL,
243
244 INC_R,
245 INC_INDIRECT_HL,
246 DEC_R,
247 DEC_INDIRECT_HL,
248
249 /* 16-bit arithmetic group. */
250
251 ADD_HL_RR,
252
253 ADC_HL_RR,
254 SBC_HL_RR,
255
256 INC_RR,
257 DEC_RR,
258
259 /* General-purpose arithmetic and CPU control group. */
260
261 DAA,
262
263 CPL,
264 NEG,
265
266 CCF,
267 SCF,
268
269 NOP,
270 HALT,
271
272 DI,
273 EI,
274
275 IM_N,
276
277 /* Rotate and shift group. */
278
279 RLCA,
280 RLA,
281 RRCA,
282 RRA,
283
284 RLC_R,
285 RLC_INDIRECT_HL,
286 RL_R,
287 RL_INDIRECT_HL,
288 RRC_R,
289 RRC_INDIRECT_HL,
290 RR_R,
291 RR_INDIRECT_HL,
292 SLA_R,
293 SLA_INDIRECT_HL,
294 SLL_R,
295 SLL_INDIRECT_HL,
296 SRA_R,
297 SRA_INDIRECT_HL,
298 SRL_R,
299 SRL_INDIRECT_HL,
300
301 RLD_RRD, /* Handle "RLD" and "RRD". */
302
303 /* Bit set, reset, and test group. */
304
305 BIT_B_R,
306 BIT_B_INDIRECT_HL,
307 SET_B_R,
308 SET_B_INDIRECT_HL,
309 RES_B_R,
310 RES_B_INDIRECT_HL,
311
312 /* Jump group. */
313
314 JP_NN,
315 JP_CC_NN,
316 JR_E,
317 JR_DD_E,
318 JP_HL,
319 DJNZ_E,
320
321 /* Call and return group. */
322
323 CALL_NN,
324 CALL_CC_NN,
325 RET,
326 RET_CC,
327
328 RETI_RETN, /* Handle "RETI" and "RETN". */
329
330 RST_P,
331
332 /* Input and output group. */
333
334 IN_A_N,
335 IN_R_C, /* Correctly handle undocumented "IN F, (C)"
336 * instruction.
337 */
338
339 INI_IND, /* Handle "INI" and "IND". */
340 INIR_INDR, /* Handle "INIR" and "INDR". */
341
342 OUT_N_A,
343 OUT_C_R, /* Correctly handle undocumented "OUT (C), 0"
344 * instruction.
345 */
346
347 OUTI_OUTD, /* Handle "OUTI" and "OUTD".*/
348 OTIR_OTDR, /* Handle "OTIR" and "OTDR". */
349
350 /* Prefix group. */
351
352 CB_PREFIX,
353 DD_PREFIX,
354 FD_PREFIX,
355 ED_PREFIX,
356
357 /* Special instruction group. */
358
359 ED_UNDEFINED /* ED_UNDEFINED is used to catch undefined
360 * 0xed prefixed opcodes.
361 */
362
363};
364
365
366
367
368/* Shortcuts for flags and registers. */
369
370#define SZC_FLAGS (Z80_S_FLAG | Z80_Z_FLAG | Z80_C_FLAG)
371#define YX_FLAGS (Z80_Y_FLAG | Z80_X_FLAG)
372#define SZ_FLAGS (Z80_S_FLAG | Z80_Z_FLAG)
373#define SZPV_FLAGS (Z80_S_FLAG | Z80_Z_FLAG | Z80_PV_FLAG)
374#define SYX_FLAGS (Z80_S_FLAG | Z80_Y_FLAG | Z80_X_FLAG)
375#define HC_FLAGS (Z80_H_FLAG | Z80_C_FLAG)
376
377#define A (state.registers.byte[Z80_A])
378#define F (state.registers.byte[Z80_F])
379#define B (state.registers.byte[Z80_B])
380#define C (state.registers.byte[Z80_C])
381
382#define AF (state.registers.word[Z80_AF])
383#define BC (state.registers.word[Z80_BC])
384#define DE (state.registers.word[Z80_DE])
385#define HL (state.registers.word[Z80_HL])
386#define SP (state.registers.word[Z80_SP])
387
388#define HL_IX_IY *((unsigned short *) registers[6])
389
390/* Opcode decoding macros. Y() is bits 5-3 of the opcode, Z() is bits 2-0,
391 * P() bits 5-4, and Q() bits 4-3.
392 */
393
394#define Y(opcode) (((opcode) >> 3) & 0x07)
395#define Z(opcode) ((opcode) & 0x07)
396#define P(opcode) (((opcode) >> 4) & 0x03)
397#define Q(opcode) (((opcode) >> 3) & 0x03)
398
399/* Registers and conditions are decoded using tables in encodings.h. S() is
400 * for the special cases "LD H/L, (IX/Y + d)" and "LD (IX/Y + d), H/L".
401 */
402
403#define R(r) *((unsigned char *) (registers[(r)]))
404#define S(s) *((unsigned char *) state.register_table[(s)])
405#define RR(rr) *((unsigned short *) registers[(rr) + 8])
406#define SS(ss) *((unsigned short *) registers[(ss) + 12])
407#define CC(cc) ((F ^ XOR_CONDITION_TABLE[(cc)]) \
408& AND_CONDITION_TABLE[(cc)])
409#define DD(dd) CC(dd)
410
411/* Macros to read constants, displacements, or addresses from code. */
412
413#define READ_N(n) \
414{ \
415Z80_FETCH_BYTE(pc, (n)); \
416pc++; \
417elapsed_cycles += 3; \
418}
419
420#define READ_NN(nn) \
421{ \
422Z80_FETCH_WORD(pc, (nn)); \
423pc += 2; \
424elapsed_cycles += 6; \
425}
426
427#define READ_D(d) \
428{ \
429Z80_FETCH_BYTE(pc, (d)); \
430(d) = (signed char) (d); \
431pc++; \
432elapsed_cycles += 3; \
433}
434
435/* Macros to read and write data. */
436
437#define READ_BYTE(address, x) \
438{ \
439Z80_READ_BYTE((address), (x)); \
440elapsed_cycles += 3; \
441}
442
443#define WRITE_BYTE(address, x) \
444{ \
445Z80_WRITE_BYTE((address), (x)); \
446elapsed_cycles += 3; \
447}
448
449#define READ_WORD(address, x) \
450{ \
451Z80_READ_WORD((address), (x)); \
452elapsed_cycles += 6; \
453}
454
455#define WRITE_WORD(address, x) \
456{ \
457Z80_WRITE_WORD((address), (x)); \
458elapsed_cycles += 6; \
459}
460
461/* Indirect (HL) and indexed (IX + d) or (IY + d) memory operands read and
462 * write macros.
463 */
464
465#define READ_INDIRECT_HL(x) \
466{ \
467if (registers == state.register_table) { \
468\
469READ_BYTE(HL, (x)); \
470\
471} else { \
472\
473int d; \
474\
475READ_D(d); \
476d += HL_IX_IY; \
477READ_BYTE(d, (x)); \
478\
479elapsed_cycles += 5; \
480\
481} \
482}
483
484#define WRITE_INDIRECT_HL(x) \
485{ \
486if (registers == state.register_table) { \
487\
488WRITE_BYTE(HL, (x)); \
489\
490} else { \
491\
492int d; \
493\
494READ_D(d); \
495d += HL_IX_IY; \
496WRITE_BYTE(d, (x)); \
497\
498elapsed_cycles += 5; \
499\
500} \
501}
502
503/* Stack operation macros. */
504
505#define PUSH(x) \
506{ \
507SP -= 2; \
508WRITE_WORD(SP, (x)); \
509}
510
511#define POP(x) \
512{ \
513READ_WORD(SP, (x)); \
514SP += 2; \
515}
516
517/* Exchange macro. */
518
519#define EXCHANGE(a, b) \
520{ \
521int t; \
522\
523t = (a); \
524(a) = (b); \
525(b) = t; \
526}
527
528/* 8-bit arithmetic and logic operations. */
529
530#define ADD(x) \
531{ \
532int a, z, c, f; \
533\
534a = A; \
535z = a + (x); \
536\
537c = a ^ (x) ^ z; \
538f = c & Z80_H_FLAG; \
539f |= SZYX_FLAGS_TABLE[z & 0xff]; \
540f |= OVERFLOW_TABLE[c >> 7]; \
541f |= z >> (8 - Z80_C_FLAG_SHIFT); \
542\
543A = z; \
544F = f; \
545}
546
547#define ADC(x) \
548{ \
549int a, z, c, f; \
550\
551a = A; \
552z = a + (x) + (F & Z80_C_FLAG); \
553\
554c = a ^ (x) ^ z; \
555f = c & Z80_H_FLAG; \
556f |= SZYX_FLAGS_TABLE[z & 0xff]; \
557f |= OVERFLOW_TABLE[c >> 7]; \
558f |= z >> (8 - Z80_C_FLAG_SHIFT); \
559\
560A = z; \
561F = f; \
562}
563
564#define SUB(x) \
565{ \
566int a, z, c, f; \
567\
568a = A; \
569z = a - (x); \
570\
571c = a ^ (x) ^ z; \
572f = Z80_N_FLAG | (c & Z80_H_FLAG); \
573f |= SZYX_FLAGS_TABLE[z & 0xff]; \
574c &= 0x0180; \
575f |= OVERFLOW_TABLE[c >> 7]; \
576f |= c >> (8 - Z80_C_FLAG_SHIFT); \
577\
578A = z; \
579F = f; \
580}
581
582#define SBC(x) \
583{ \
584int a, z, c, f; \
585\
586a = A; \
587z = a - (x) - (F & Z80_C_FLAG); \
588\
589c = a ^ (x) ^ z; \
590f = Z80_N_FLAG | (c & Z80_H_FLAG); \
591f |= SZYX_FLAGS_TABLE[z & 0xff]; \
592c &= 0x0180; \
593f |= OVERFLOW_TABLE[c >> 7]; \
594f |= c >> (8 - Z80_C_FLAG_SHIFT); \
595\
596A = z; \
597F = f; \
598}
599
600#define AND(x) \
601{ \
602F = SZYXP_FLAGS_TABLE[A &= (x)] | Z80_H_FLAG; \
603}
604
605#define OR(x) \
606{ \
607F = SZYXP_FLAGS_TABLE[A |= (x)]; \
608}
609
610#define XOR(x) \
611{ \
612F = SZYXP_FLAGS_TABLE[A ^= (x)]; \
613}
614
615#define CP(x) \
616{ \
617int a, z, c, f; \
618\
619a = A; \
620z = a - (x); \
621\
622c = a ^ (x) ^ z; \
623f = Z80_N_FLAG | (c & Z80_H_FLAG); \
624f |= SZYX_FLAGS_TABLE[z & 0xff] & SZ_FLAGS; \
625f |= (x) & YX_FLAGS; \
626c &= 0x0180; \
627f |= OVERFLOW_TABLE[c >> 7]; \
628f |= c >> (8 - Z80_C_FLAG_SHIFT); \
629\
630F = f; \
631}
632
633#define INC(x) \
634{ \
635int z, c, f; \
636\
637z = (x) + 1; \
638c = (x) ^ z; \
639\
640f = F & Z80_C_FLAG; \
641f |= c & Z80_H_FLAG; \
642f |= SZYX_FLAGS_TABLE[z & 0xff]; \
643f |= OVERFLOW_TABLE[(c >> 7) & 0x03]; \
644\
645(x) = z; \
646F = f; \
647}
648
649#define DEC(x) \
650{ \
651int z, c, f; \
652\
653z = (x) - 1; \
654c = (x) ^ z; \
655\
656f = Z80_N_FLAG | (F & Z80_C_FLAG); \
657f |= c & Z80_H_FLAG; \
658f |= SZYX_FLAGS_TABLE[z & 0xff]; \
659f |= OVERFLOW_TABLE[(c >> 7) & 0x03]; \
660\
661(x) = z; \
662F = f; \
663}
664
665/* 0xcb prefixed logical operations. */
666
667#define RLC(x) \
668{ \
669int c; \
670\
671c = (x) >> 7; \
672(x) = ((x) << 1) | c; \
673F = SZYXP_FLAGS_TABLE[(x) & 0xff] | c; \
674}
675
676#define RL(x) \
677{ \
678int c; \
679\
680c = (x) >> 7; \
681(x) = ((x) << 1) | (F & Z80_C_FLAG); \
682F = SZYXP_FLAGS_TABLE[(x) & 0xff] | c; \
683}
684
685#define RRC(x) \
686{ \
687int c; \
688\
689c = (x) & 0x01; \
690(x) = ((x) >> 1) | (c << 7); \
691F = SZYXP_FLAGS_TABLE[(x) & 0xff] | c; \
692}
693
694#define RR_INSTRUCTION(x) \
695{ \
696int c; \
697\
698c = (x) & 0x01; \
699(x) = ((x) >> 1) | ((F & Z80_C_FLAG) << 7); \
700F = SZYXP_FLAGS_TABLE[(x) & 0xff] | c; \
701}
702
703#define SLA(x) \
704{ \
705int c; \
706\
707c = (x) >> 7; \
708(x) <<= 1; \
709F = SZYXP_FLAGS_TABLE[(x) & 0xff] | c; \
710}
711
712#define SLL(x) \
713{ \
714int c; \
715\
716c = (x) >> 7; \
717(x) = ((x) << 1) | 0x01; \
718F = SZYXP_FLAGS_TABLE[(x) & 0xff] | c; \
719}
720
721#define SRA(x) \
722{ \
723int c; \
724\
725c = (x) & 0x01; \
726(x) = ((signed char) (x)) >> 1; \
727F = SZYXP_FLAGS_TABLE[(x) & 0xff] | c; \
728}
729
730#define SRL(x) \
731{ \
732int c; \
733\
734c = (x) & 0x01; \
735(x) >>= 1; \
736F = SZYXP_FLAGS_TABLE[(x) & 0xff] | c; \
737}
738
739
740
741
742
743/* Generated file, see maketables.c. */
744
745static const unsigned char INSTRUCTION_TABLE[256] = {
746
747 NOP,
748 LD_RR_NN,
749 LD_INDIRECT_BC_A,
750 INC_RR,
751 INC_R,
752 DEC_R,
753 LD_R_N,
754 RLCA,
755
756 EX_AF_AF_PRIME,
757 ADD_HL_RR,
758 LD_A_INDIRECT_BC,
759 DEC_RR,
760 INC_R,
761 DEC_R,
762 LD_R_N,
763 RRCA,
764
765 DJNZ_E,
766 LD_RR_NN,
767 LD_INDIRECT_DE_A,
768 INC_RR,
769 INC_R,
770 DEC_R,
771 LD_R_N,
772 RLA,
773
774 JR_E,
775 ADD_HL_RR,
776 LD_A_INDIRECT_DE,
777 DEC_RR,
778 INC_R,
779 DEC_R,
780 LD_R_N,
781 RRA,
782
783 JR_DD_E,
784 LD_RR_NN,
785 LD_INDIRECT_NN_HL,
786 INC_RR,
787 INC_R,
788 DEC_R,
789 LD_R_N,
790 DAA,
791
792 JR_DD_E,
793 ADD_HL_RR,
794 LD_HL_INDIRECT_NN,
795 DEC_RR,
796 INC_R,
797 DEC_R,
798 LD_R_N,
799 CPL,
800
801 JR_DD_E,
802 LD_RR_NN,
803 LD_INDIRECT_NN_A,
804 INC_RR,
805 INC_INDIRECT_HL,
806 DEC_INDIRECT_HL,
807 LD_INDIRECT_HL_N,
808 SCF,
809
810 JR_DD_E,
811 ADD_HL_RR,
812 LD_A_INDIRECT_NN,
813 DEC_RR,
814 INC_R,
815 DEC_R,
816 LD_R_N,
817 CCF,
818
819 NOP,
820 LD_R_R,
821 LD_R_R,
822 LD_R_R,
823 LD_R_R,
824 LD_R_R,
825 LD_R_INDIRECT_HL,
826 LD_R_R,
827
828 LD_R_R,
829 NOP,
830 LD_R_R,
831 LD_R_R,
832 LD_R_R,
833 LD_R_R,
834 LD_R_INDIRECT_HL,
835 LD_R_R,
836
837 LD_R_R,
838 LD_R_R,
839 NOP,
840 LD_R_R,
841 LD_R_R,
842 LD_R_R,
843 LD_R_INDIRECT_HL,
844 LD_R_R,
845
846 LD_R_R,
847 LD_R_R,
848 LD_R_R,
849 NOP,
850 LD_R_R,
851 LD_R_R,
852 LD_R_INDIRECT_HL,
853 LD_R_R,
854
855 LD_R_R,
856 LD_R_R,
857 LD_R_R,
858 LD_R_R,
859 NOP,
860 LD_R_R,
861 LD_R_INDIRECT_HL,
862 LD_R_R,
863
864 LD_R_R,
865 LD_R_R,
866 LD_R_R,
867 LD_R_R,
868 LD_R_R,
869 NOP,
870 LD_R_INDIRECT_HL,
871 LD_R_R,
872
873 LD_INDIRECT_HL_R,
874 LD_INDIRECT_HL_R,
875 LD_INDIRECT_HL_R,
876 LD_INDIRECT_HL_R,
877 LD_INDIRECT_HL_R,
878 LD_INDIRECT_HL_R,
879 HALT,
880 LD_INDIRECT_HL_R,
881
882 LD_R_R,
883 LD_R_R,
884 LD_R_R,
885 LD_R_R,
886 LD_R_R,
887 LD_R_R,
888 LD_R_INDIRECT_HL,
889 NOP,
890
891 ADD_R,
892 ADD_R,
893 ADD_R,
894 ADD_R,
895 ADD_R,
896 ADD_R,
897 ADD_INDIRECT_HL,
898 ADD_R,
899
900 ADC_R,
901 ADC_R,
902 ADC_R,
903 ADC_R,
904 ADC_R,
905 ADC_R,
906 ADC_INDIRECT_HL,
907 ADC_R,
908
909 SUB_R,
910 SUB_R,
911 SUB_R,
912 SUB_R,
913 SUB_R,
914 SUB_R,
915 SUB_INDIRECT_HL,
916 SUB_R,
917
918 SBC_R,
919 SBC_R,
920 SBC_R,
921 SBC_R,
922 SBC_R,
923 SBC_R,
924 SBC_INDIRECT_HL,
925 SBC_R,
926
927 AND_R,
928 AND_R,
929 AND_R,
930 AND_R,
931 AND_R,
932 AND_R,
933 AND_INDIRECT_HL,
934 AND_R,
935
936 XOR_R,
937 XOR_R,
938 XOR_R,
939 XOR_R,
940 XOR_R,
941 XOR_R,
942 XOR_INDIRECT_HL,
943 XOR_R,
944
945 OR_R,
946 OR_R,
947 OR_R,
948 OR_R,
949 OR_R,
950 OR_R,
951 OR_INDIRECT_HL,
952 OR_R,
953
954 CP_R,
955 CP_R,
956 CP_R,
957 CP_R,
958 CP_R,
959 CP_R,
960 CP_INDIRECT_HL,
961 CP_R,
962
963 RET_CC,
964 POP_SS,
965 JP_CC_NN,
966 JP_NN,
967 CALL_CC_NN,
968 PUSH_SS,
969 ADD_N,
970 RST_P,
971
972 RET_CC,
973 RET,
974 JP_CC_NN,
975 CB_PREFIX,
976 CALL_CC_NN,
977 CALL_NN,
978 ADC_N,
979 RST_P,
980
981 RET_CC,
982 POP_SS,
983 JP_CC_NN,
984 OUT_N_A,
985 CALL_CC_NN,
986 PUSH_SS,
987 SUB_N,
988 RST_P,
989
990 RET_CC,
991 EXX,
992 JP_CC_NN,
993 IN_A_N,
994 CALL_CC_NN,
995 DD_PREFIX,
996 SBC_N,
997 RST_P,
998
999 RET_CC,
1000 POP_SS,
1001 JP_CC_NN,
1002 EX_INDIRECT_SP_HL,
1003 CALL_CC_NN,
1004 PUSH_SS,
1005 AND_N,
1006 RST_P,
1007
1008 RET_CC,
1009 JP_HL,
1010 JP_CC_NN,
1011 EX_DE_HL,
1012 CALL_CC_NN,
1013 ED_PREFIX,
1014 XOR_N,
1015 RST_P,
1016
1017 RET_CC,
1018 POP_SS,
1019 JP_CC_NN,
1020 DI,
1021 CALL_CC_NN,
1022 PUSH_SS,
1023 OR_N,
1024 RST_P,
1025
1026 RET_CC,
1027 LD_SP_HL,
1028 JP_CC_NN,
1029 EI,
1030 CALL_CC_NN,
1031 FD_PREFIX,
1032 CP_N,
1033 RST_P,
1034
1035};
1036
1037
1038static const unsigned char CB_INSTRUCTION_TABLE[256] = {
1039
1040 RLC_R,
1041 RLC_R,
1042 RLC_R,
1043 RLC_R,
1044 RLC_R,
1045 RLC_R,
1046 RLC_INDIRECT_HL,
1047 RLC_R,
1048
1049 RRC_R,
1050 RRC_R,
1051 RRC_R,
1052 RRC_R,
1053 RRC_R,
1054 RRC_R,
1055 RRC_INDIRECT_HL,
1056 RRC_R,
1057
1058 RL_R,
1059 RL_R,
1060 RL_R,
1061 RL_R,
1062 RL_R,
1063 RL_R,
1064 RL_INDIRECT_HL,
1065 RL_R,
1066
1067 RR_R,
1068 RR_R,
1069 RR_R,
1070 RR_R,
1071 RR_R,
1072 RR_R,
1073 RR_INDIRECT_HL,
1074 RR_R,
1075
1076 SLA_R,
1077 SLA_R,
1078 SLA_R,
1079 SLA_R,
1080 SLA_R,
1081 SLA_R,
1082 SLA_INDIRECT_HL,
1083 SLA_R,
1084
1085 SRA_R,
1086 SRA_R,
1087 SRA_R,
1088 SRA_R,
1089 SRA_R,
1090 SRA_R,
1091 SRA_INDIRECT_HL,
1092 SRA_R,
1093
1094 SLL_R,
1095 SLL_R,
1096 SLL_R,
1097 SLL_R,
1098 SLL_R,
1099 SLL_R,
1100 SLL_INDIRECT_HL,
1101 SLL_R,
1102
1103 SRL_R,
1104 SRL_R,
1105 SRL_R,
1106 SRL_R,
1107 SRL_R,
1108 SRL_R,
1109 SRL_INDIRECT_HL,
1110 SRL_R,
1111
1112 BIT_B_R,
1113 BIT_B_R,
1114 BIT_B_R,
1115 BIT_B_R,
1116 BIT_B_R,
1117 BIT_B_R,
1118 BIT_B_INDIRECT_HL,
1119 BIT_B_R,
1120
1121 BIT_B_R,
1122 BIT_B_R,
1123 BIT_B_R,
1124 BIT_B_R,
1125 BIT_B_R,
1126 BIT_B_R,
1127 BIT_B_INDIRECT_HL,
1128 BIT_B_R,
1129
1130 BIT_B_R,
1131 BIT_B_R,
1132 BIT_B_R,
1133 BIT_B_R,
1134 BIT_B_R,
1135 BIT_B_R,
1136 BIT_B_INDIRECT_HL,
1137 BIT_B_R,
1138
1139 BIT_B_R,
1140 BIT_B_R,
1141 BIT_B_R,
1142 BIT_B_R,
1143 BIT_B_R,
1144 BIT_B_R,
1145 BIT_B_INDIRECT_HL,
1146 BIT_B_R,
1147
1148 BIT_B_R,
1149 BIT_B_R,
1150 BIT_B_R,
1151 BIT_B_R,
1152 BIT_B_R,
1153 BIT_B_R,
1154 BIT_B_INDIRECT_HL,
1155 BIT_B_R,
1156
1157 BIT_B_R,
1158 BIT_B_R,
1159 BIT_B_R,
1160 BIT_B_R,
1161 BIT_B_R,
1162 BIT_B_R,
1163 BIT_B_INDIRECT_HL,
1164 BIT_B_R,
1165
1166 BIT_B_R,
1167 BIT_B_R,
1168 BIT_B_R,
1169 BIT_B_R,
1170 BIT_B_R,
1171 BIT_B_R,
1172 BIT_B_INDIRECT_HL,
1173 BIT_B_R,
1174
1175 BIT_B_R,
1176 BIT_B_R,
1177 BIT_B_R,
1178 BIT_B_R,
1179 BIT_B_R,
1180 BIT_B_R,
1181 BIT_B_INDIRECT_HL,
1182 BIT_B_R,
1183
1184 RES_B_R,
1185 RES_B_R,
1186 RES_B_R,
1187 RES_B_R,
1188 RES_B_R,
1189 RES_B_R,
1190 RES_B_INDIRECT_HL,
1191 RES_B_R,
1192
1193 RES_B_R,
1194 RES_B_R,
1195 RES_B_R,
1196 RES_B_R,
1197 RES_B_R,
1198 RES_B_R,
1199 RES_B_INDIRECT_HL,
1200 RES_B_R,
1201
1202 RES_B_R,
1203 RES_B_R,
1204 RES_B_R,
1205 RES_B_R,
1206 RES_B_R,
1207 RES_B_R,
1208 RES_B_INDIRECT_HL,
1209 RES_B_R,
1210
1211 RES_B_R,
1212 RES_B_R,
1213 RES_B_R,
1214 RES_B_R,
1215 RES_B_R,
1216 RES_B_R,
1217 RES_B_INDIRECT_HL,
1218 RES_B_R,
1219
1220 RES_B_R,
1221 RES_B_R,
1222 RES_B_R,
1223 RES_B_R,
1224 RES_B_R,
1225 RES_B_R,
1226 RES_B_INDIRECT_HL,
1227 RES_B_R,
1228
1229 RES_B_R,
1230 RES_B_R,
1231 RES_B_R,
1232 RES_B_R,
1233 RES_B_R,
1234 RES_B_R,
1235 RES_B_INDIRECT_HL,
1236 RES_B_R,
1237
1238 RES_B_R,
1239 RES_B_R,
1240 RES_B_R,
1241 RES_B_R,
1242 RES_B_R,
1243 RES_B_R,
1244 RES_B_INDIRECT_HL,
1245 RES_B_R,
1246
1247 RES_B_R,
1248 RES_B_R,
1249 RES_B_R,
1250 RES_B_R,
1251 RES_B_R,
1252 RES_B_R,
1253 RES_B_INDIRECT_HL,
1254 RES_B_R,
1255
1256 SET_B_R,
1257 SET_B_R,
1258 SET_B_R,
1259 SET_B_R,
1260 SET_B_R,
1261 SET_B_R,
1262 SET_B_INDIRECT_HL,
1263 SET_B_R,
1264
1265 SET_B_R,
1266 SET_B_R,
1267 SET_B_R,
1268 SET_B_R,
1269 SET_B_R,
1270 SET_B_R,
1271 SET_B_INDIRECT_HL,
1272 SET_B_R,
1273
1274 SET_B_R,
1275 SET_B_R,
1276 SET_B_R,
1277 SET_B_R,
1278 SET_B_R,
1279 SET_B_R,
1280 SET_B_INDIRECT_HL,
1281 SET_B_R,
1282
1283 SET_B_R,
1284 SET_B_R,
1285 SET_B_R,
1286 SET_B_R,
1287 SET_B_R,
1288 SET_B_R,
1289 SET_B_INDIRECT_HL,
1290 SET_B_R,
1291
1292 SET_B_R,
1293 SET_B_R,
1294 SET_B_R,
1295 SET_B_R,
1296 SET_B_R,
1297 SET_B_R,
1298 SET_B_INDIRECT_HL,
1299 SET_B_R,
1300
1301 SET_B_R,
1302 SET_B_R,
1303 SET_B_R,
1304 SET_B_R,
1305 SET_B_R,
1306 SET_B_R,
1307 SET_B_INDIRECT_HL,
1308 SET_B_R,
1309
1310 SET_B_R,
1311 SET_B_R,
1312 SET_B_R,
1313 SET_B_R,
1314 SET_B_R,
1315 SET_B_R,
1316 SET_B_INDIRECT_HL,
1317 SET_B_R,
1318
1319 SET_B_R,
1320 SET_B_R,
1321 SET_B_R,
1322 SET_B_R,
1323 SET_B_R,
1324 SET_B_R,
1325 SET_B_INDIRECT_HL,
1326 SET_B_R,
1327
1328};
1329
1330
1331static const unsigned char ED_INSTRUCTION_TABLE[256] = {
1332
1333 ED_UNDEFINED,
1334 ED_UNDEFINED,
1335 ED_UNDEFINED,
1336 ED_UNDEFINED,
1337 ED_UNDEFINED,
1338 ED_UNDEFINED,
1339 ED_UNDEFINED,
1340 ED_UNDEFINED,
1341
1342 ED_UNDEFINED,
1343 ED_UNDEFINED,
1344 ED_UNDEFINED,
1345 ED_UNDEFINED,
1346 ED_UNDEFINED,
1347 ED_UNDEFINED,
1348 ED_UNDEFINED,
1349 ED_UNDEFINED,
1350
1351 ED_UNDEFINED,
1352 ED_UNDEFINED,
1353 ED_UNDEFINED,
1354 ED_UNDEFINED,
1355 ED_UNDEFINED,
1356 ED_UNDEFINED,
1357 ED_UNDEFINED,
1358 ED_UNDEFINED,
1359
1360 ED_UNDEFINED,
1361 ED_UNDEFINED,
1362 ED_UNDEFINED,
1363 ED_UNDEFINED,
1364 ED_UNDEFINED,
1365 ED_UNDEFINED,
1366 ED_UNDEFINED,
1367 ED_UNDEFINED,
1368
1369 ED_UNDEFINED,
1370 ED_UNDEFINED,
1371 ED_UNDEFINED,
1372 ED_UNDEFINED,
1373 ED_UNDEFINED,
1374 ED_UNDEFINED,
1375 ED_UNDEFINED,
1376 ED_UNDEFINED,
1377
1378 ED_UNDEFINED,
1379 ED_UNDEFINED,
1380 ED_UNDEFINED,
1381 ED_UNDEFINED,
1382 ED_UNDEFINED,
1383 ED_UNDEFINED,
1384 ED_UNDEFINED,
1385 ED_UNDEFINED,
1386
1387 ED_UNDEFINED,
1388 ED_UNDEFINED,
1389 ED_UNDEFINED,
1390 ED_UNDEFINED,
1391 ED_UNDEFINED,
1392 ED_UNDEFINED,
1393 ED_UNDEFINED,
1394 ED_UNDEFINED,
1395
1396 ED_UNDEFINED,
1397 ED_UNDEFINED,
1398 ED_UNDEFINED,
1399 ED_UNDEFINED,
1400 ED_UNDEFINED,
1401 ED_UNDEFINED,
1402 ED_UNDEFINED,
1403 ED_UNDEFINED,
1404
1405 IN_R_C,
1406 OUT_C_R,
1407 SBC_HL_RR,
1408 LD_INDIRECT_NN_RR,
1409 NEG,
1410 RETI_RETN,
1411 IM_N,
1412 LD_I_A_LD_R_A,
1413
1414 IN_R_C,
1415 OUT_C_R,
1416 ADC_HL_RR,
1417 LD_RR_INDIRECT_NN,
1418 NEG,
1419 RETI_RETN,
1420 IM_N,
1421 LD_I_A_LD_R_A,
1422
1423 IN_R_C,
1424 OUT_C_R,
1425 SBC_HL_RR,
1426 LD_INDIRECT_NN_RR,
1427 NEG,
1428 RETI_RETN,
1429 IM_N,
1430 LD_A_I_LD_A_R,
1431
1432 IN_R_C,
1433 OUT_C_R,
1434 ADC_HL_RR,
1435 LD_RR_INDIRECT_NN,
1436 NEG,
1437 RETI_RETN,
1438 IM_N,
1439 LD_A_I_LD_A_R,
1440
1441 IN_R_C,
1442 OUT_C_R,
1443 SBC_HL_RR,
1444 LD_INDIRECT_NN_RR,
1445 NEG,
1446 RETI_RETN,
1447 IM_N,
1448 RLD_RRD,
1449
1450 IN_R_C,
1451 OUT_C_R,
1452 ADC_HL_RR,
1453 LD_RR_INDIRECT_NN,
1454 NEG,
1455 RETI_RETN,
1456 IM_N,
1457 RLD_RRD,
1458
1459 IN_R_C,
1460 OUT_C_R,
1461 SBC_HL_RR,
1462 LD_INDIRECT_NN_RR,
1463 NEG,
1464 RETI_RETN,
1465 IM_N,
1466 ED_UNDEFINED,
1467
1468 IN_R_C,
1469 OUT_C_R,
1470 ADC_HL_RR,
1471 LD_RR_INDIRECT_NN,
1472 NEG,
1473 RETI_RETN,
1474 IM_N,
1475 ED_UNDEFINED,
1476
1477 ED_UNDEFINED,
1478 ED_UNDEFINED,
1479 ED_UNDEFINED,
1480 ED_UNDEFINED,
1481 ED_UNDEFINED,
1482 ED_UNDEFINED,
1483 ED_UNDEFINED,
1484 ED_UNDEFINED,
1485
1486 ED_UNDEFINED,
1487 ED_UNDEFINED,
1488 ED_UNDEFINED,
1489 ED_UNDEFINED,
1490 ED_UNDEFINED,
1491 ED_UNDEFINED,
1492 ED_UNDEFINED,
1493 ED_UNDEFINED,
1494
1495 ED_UNDEFINED,
1496 ED_UNDEFINED,
1497 ED_UNDEFINED,
1498 ED_UNDEFINED,
1499 ED_UNDEFINED,
1500 ED_UNDEFINED,
1501 ED_UNDEFINED,
1502 ED_UNDEFINED,
1503
1504 ED_UNDEFINED,
1505 ED_UNDEFINED,
1506 ED_UNDEFINED,
1507 ED_UNDEFINED,
1508 ED_UNDEFINED,
1509 ED_UNDEFINED,
1510 ED_UNDEFINED,
1511 ED_UNDEFINED,
1512
1513 LDI_LDD,
1514 CPI_CPD,
1515 INI_IND,
1516 OUTI_OUTD,
1517 ED_UNDEFINED,
1518 ED_UNDEFINED,
1519 ED_UNDEFINED,
1520 ED_UNDEFINED,
1521
1522 LDI_LDD,
1523 CPI_CPD,
1524 INI_IND,
1525 OUTI_OUTD,
1526 ED_UNDEFINED,
1527 ED_UNDEFINED,
1528 ED_UNDEFINED,
1529 ED_UNDEFINED,
1530
1531 LDIR_LDDR,
1532 CPIR_CPDR,
1533 INIR_INDR,
1534 OTIR_OTDR,
1535 ED_UNDEFINED,
1536 ED_UNDEFINED,
1537 ED_UNDEFINED,
1538 ED_UNDEFINED,
1539
1540 LDIR_LDDR,
1541 CPIR_CPDR,
1542 INIR_INDR,
1543 OTIR_OTDR,
1544 ED_UNDEFINED,
1545 ED_UNDEFINED,
1546 ED_UNDEFINED,
1547 ED_UNDEFINED,
1548
1549 ED_UNDEFINED,
1550 ED_UNDEFINED,
1551 ED_UNDEFINED,
1552 ED_UNDEFINED,
1553 ED_UNDEFINED,
1554 ED_UNDEFINED,
1555 ED_UNDEFINED,
1556 ED_UNDEFINED,
1557
1558 ED_UNDEFINED,
1559 ED_UNDEFINED,
1560 ED_UNDEFINED,
1561 ED_UNDEFINED,
1562 ED_UNDEFINED,
1563 ED_UNDEFINED,
1564 ED_UNDEFINED,
1565 ED_UNDEFINED,
1566
1567 ED_UNDEFINED,
1568 ED_UNDEFINED,
1569 ED_UNDEFINED,
1570 ED_UNDEFINED,
1571 ED_UNDEFINED,
1572 ED_UNDEFINED,
1573 ED_UNDEFINED,
1574 ED_UNDEFINED,
1575
1576 ED_UNDEFINED,
1577 ED_UNDEFINED,
1578 ED_UNDEFINED,
1579 ED_UNDEFINED,
1580 ED_UNDEFINED,
1581 ED_UNDEFINED,
1582 ED_UNDEFINED,
1583 ED_UNDEFINED,
1584
1585 ED_UNDEFINED,
1586 ED_UNDEFINED,
1587 ED_UNDEFINED,
1588 ED_UNDEFINED,
1589 ED_UNDEFINED,
1590 ED_UNDEFINED,
1591 ED_UNDEFINED,
1592 ED_UNDEFINED,
1593
1594 ED_UNDEFINED,
1595 ED_UNDEFINED,
1596 ED_UNDEFINED,
1597 ED_UNDEFINED,
1598 ED_UNDEFINED,
1599 ED_UNDEFINED,
1600 ED_UNDEFINED,
1601 ED_UNDEFINED,
1602
1603 ED_UNDEFINED,
1604 ED_UNDEFINED,
1605 ED_UNDEFINED,
1606 ED_UNDEFINED,
1607 ED_UNDEFINED,
1608 ED_UNDEFINED,
1609 ED_UNDEFINED,
1610 ED_UNDEFINED,
1611
1612 ED_UNDEFINED,
1613 ED_UNDEFINED,
1614 ED_UNDEFINED,
1615 ED_UNDEFINED,
1616 ED_UNDEFINED,
1617 ED_UNDEFINED,
1618 ED_UNDEFINED,
1619 ED_UNDEFINED,
1620
1621};
1622
1623static const unsigned char SZYX_FLAGS_TABLE[256] = {
1624
1625 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1626 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
1627 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1628 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
1629 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
1630 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
1631 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
1632 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
1633 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1634 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
1635 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1636 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
1637 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
1638 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
1639 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
1640 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
1641 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
1642 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
1643 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
1644 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
1645 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0,
1646 0xa8, 0xa8, 0xa8, 0xa8, 0xa8, 0xa8, 0xa8, 0xa8,
1647 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0,
1648 0xa8, 0xa8, 0xa8, 0xa8, 0xa8, 0xa8, 0xa8, 0xa8,
1649 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
1650 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
1651 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
1652 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
1653 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0,
1654 0xa8, 0xa8, 0xa8, 0xa8, 0xa8, 0xa8, 0xa8, 0xa8,
1655 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0,
1656 0xa8, 0xa8, 0xa8, 0xa8, 0xa8, 0xa8, 0xa8, 0xa8,
1657
1658};
1659
1660static const unsigned char SZYXP_FLAGS_TABLE[256] = {
1661
1662 0x44, 0x00, 0x00, 0x04, 0x00, 0x04, 0x04, 0x00,
1663 0x08, 0x0c, 0x0c, 0x08, 0x0c, 0x08, 0x08, 0x0c,
1664 0x00, 0x04, 0x04, 0x00, 0x04, 0x00, 0x00, 0x04,
1665 0x0c, 0x08, 0x08, 0x0c, 0x08, 0x0c, 0x0c, 0x08,
1666 0x20, 0x24, 0x24, 0x20, 0x24, 0x20, 0x20, 0x24,
1667 0x2c, 0x28, 0x28, 0x2c, 0x28, 0x2c, 0x2c, 0x28,
1668 0x24, 0x20, 0x20, 0x24, 0x20, 0x24, 0x24, 0x20,
1669 0x28, 0x2c, 0x2c, 0x28, 0x2c, 0x28, 0x28, 0x2c,
1670 0x00, 0x04, 0x04, 0x00, 0x04, 0x00, 0x00, 0x04,
1671 0x0c, 0x08, 0x08, 0x0c, 0x08, 0x0c, 0x0c, 0x08,
1672 0x04, 0x00, 0x00, 0x04, 0x00, 0x04, 0x04, 0x00,
1673 0x08, 0x0c, 0x0c, 0x08, 0x0c, 0x08, 0x08, 0x0c,
1674 0x24, 0x20, 0x20, 0x24, 0x20, 0x24, 0x24, 0x20,
1675 0x28, 0x2c, 0x2c, 0x28, 0x2c, 0x28, 0x28, 0x2c,
1676 0x20, 0x24, 0x24, 0x20, 0x24, 0x20, 0x20, 0x24,
1677 0x2c, 0x28, 0x28, 0x2c, 0x28, 0x2c, 0x2c, 0x28,
1678 0x80, 0x84, 0x84, 0x80, 0x84, 0x80, 0x80, 0x84,
1679 0x8c, 0x88, 0x88, 0x8c, 0x88, 0x8c, 0x8c, 0x88,
1680 0x84, 0x80, 0x80, 0x84, 0x80, 0x84, 0x84, 0x80,
1681 0x88, 0x8c, 0x8c, 0x88, 0x8c, 0x88, 0x88, 0x8c,
1682 0xa4, 0xa0, 0xa0, 0xa4, 0xa0, 0xa4, 0xa4, 0xa0,
1683 0xa8, 0xac, 0xac, 0xa8, 0xac, 0xa8, 0xa8, 0xac,
1684 0xa0, 0xa4, 0xa4, 0xa0, 0xa4, 0xa0, 0xa0, 0xa4,
1685 0xac, 0xa8, 0xa8, 0xac, 0xa8, 0xac, 0xac, 0xa8,
1686 0x84, 0x80, 0x80, 0x84, 0x80, 0x84, 0x84, 0x80,
1687 0x88, 0x8c, 0x8c, 0x88, 0x8c, 0x88, 0x88, 0x8c,
1688 0x80, 0x84, 0x84, 0x80, 0x84, 0x80, 0x80, 0x84,
1689 0x8c, 0x88, 0x88, 0x8c, 0x88, 0x8c, 0x8c, 0x88,
1690 0xa0, 0xa4, 0xa4, 0xa0, 0xa4, 0xa0, 0xa0, 0xa4,
1691 0xac, 0xa8, 0xa8, 0xac, 0xa8, 0xac, 0xac, 0xa8,
1692 0xa4, 0xa0, 0xa0, 0xa4, 0xa0, 0xa4, 0xa4, 0xa0,
1693 0xa8, 0xac, 0xac, 0xa8, 0xac, 0xa8, 0xa8, 0xac,
1694
1695};
1696
1697
1698
1699
1700/* Indirect (HL) or prefixed indexed (IX + d) and (IY + d) memory operands are
1701 * encoded using the 3 bits "110" (0x06).
1702 */
1703
1704#define INDIRECT_HL 0x06
1705
1706
1707/* Condition codes are encoded using 2 or 3 bits. The xor table is needed for
1708 * negated conditions, it is used along with the and table.
1709 */
1710
1711static const int XOR_CONDITION_TABLE[8] = {
1712 Z80_Z_FLAG,
1713 0,
1714 Z80_C_FLAG,
1715 0,
1716 Z80_P_FLAG,
1717 0,
1718 Z80_S_FLAG,
1719 0,
1720};
1721
1722
1723static const int AND_CONDITION_TABLE[8] = {
1724 Z80_Z_FLAG,
1725 Z80_Z_FLAG,
1726 Z80_C_FLAG,
1727 Z80_C_FLAG,
1728 Z80_P_FLAG,
1729 Z80_P_FLAG,
1730 Z80_S_FLAG,
1731 Z80_S_FLAG,
1732};
1733
1734
1735/* RST instruction restart addresses, encoded by Y() bits of the opcode. */
1736
1737static const int RST_TABLE[8] = {
1738 0x00,
1739 0x08,
1740 0x10,
1741 0x18,
1742 0x20,
1743 0x28,
1744 0x30,
1745 0x38,
1746};
1747
1748
1749/* There is an overflow if the xor of the carry out and the carry of the most
1750 * significant bit is not zero.
1751 */
1752
1753static const int OVERFLOW_TABLE[4] = {
1754 0,
1755 Z80_V_FLAG,
1756 Z80_V_FLAG,
1757 0,
1758};
1759
1760
1761
1762
1763void Z80::reset()
1764{
1765 state.status = 0;
1766 AF = 0xffff;
1767 SP = 0xffff;
1768 state.i = state.pc = state.iff1 = state.iff2 = 0;
1769 state.im = Z80_INTERRUPT_MODE_0;
1770
1771 /* Build register decoding tables for both 3-bit encoded 8-bit
1772 * registers and 2-bit encoded 16-bit registers. When an opcode is
1773 * prefixed by 0xdd, HL is replaced by IX. When 0xfd prefixed, HL is
1774 * replaced by IY.
1775 */
1776
1777 /* 8-bit "R" registers. */
1778
1779 state.register_table[0] = &state.registers.byte[Z80_B];
1780 state.register_table[1] = &state.registers.byte[Z80_C];
1781 state.register_table[2] = &state.registers.byte[Z80_D];
1782 state.register_table[3] = &state.registers.byte[Z80_E];
1783 state.register_table[4] = &state.registers.byte[Z80_H];
1784 state.register_table[5] = &state.registers.byte[Z80_L];
1785
1786 /* Encoding 0x06 is used for indexed memory operands and direct HL or
1787 * IX/IY register access.
1788 */
1789
1790 state.register_table[6] = &state.registers.word[Z80_HL];
1791 state.register_table[7] = &state.registers.byte[Z80_A];
1792
1793 /* "Regular" 16-bit "RR" registers. */
1794
1795 state.register_table[8] = &state.registers.word[Z80_BC];
1796 state.register_table[9] = &state.registers.word[Z80_DE];
1797 state.register_table[10] = &state.registers.word[Z80_HL];
1798 state.register_table[11] = &state.registers.word[Z80_SP];
1799
1800 /* 16-bit "SS" registers for PUSH and POP instructions (note that SP is
1801 * replaced by AF).
1802 */
1803
1804 state.register_table[12] = &state.registers.word[Z80_BC];
1805 state.register_table[13] = &state.registers.word[Z80_DE];
1806 state.register_table[14] = &state.registers.word[Z80_HL];
1807 state.register_table[15] = &state.registers.word[Z80_AF];
1808
1809 /* 0xdd and 0xfd prefixed register decoding tables. */
1810
1811 for (int i = 0; i < 16; i++)
1812 state.dd_register_table[i] = state.fd_register_table[i] = state.register_table[i];
1813
1814 state.dd_register_table[4] = &state.registers.byte[Z80_IXH];
1815 state.dd_register_table[5] = &state.registers.byte[Z80_IXL];
1816 state.dd_register_table[6] = &state.registers.word[Z80_IX];
1817 state.dd_register_table[10] = &state.registers.word[Z80_IX];
1818 state.dd_register_table[14] = &state.registers.word[Z80_IX];
1819
1820 state.fd_register_table[4] = &state.registers.byte[Z80_IYH];
1821 state.fd_register_table[5] = &state.registers.byte[Z80_IYL];
1822 state.fd_register_table[6] = &state.registers.word[Z80_IY];
1823 state.fd_register_table[10] = &state.registers.word[Z80_IY];
1824 state.fd_register_table[14] = &state.registers.word[Z80_IY];
1825}
1826
1827
1828
1829int Z80::IRQ(int data_on_bus)
1830{
1831 state.status = 0;
1832 if (state.iff1) {
1833
1834 state.iff1 = state.iff2 = 0;
1835 state.r = (state.r & 0x80) | ((state.r + 1) & 0x7f);
1836 switch (state.im) {
1837
1838 case Z80_INTERRUPT_MODE_0: {
1839
1840 /* Assuming the opcode in data_on_bus is an
1841 * RST instruction, accepting the interrupt
1842 * should take 2 + 11 = 13 cycles.
1843 */
1844
1845 return intemulate(data_on_bus, 2);
1846
1847 }
1848
1849 case Z80_INTERRUPT_MODE_1: {
1850
1851 int elapsed_cycles;
1852
1853 elapsed_cycles = 0;
1854 SP -= 2;
1855 Z80_WRITE_WORD_INTERRUPT(SP, state.pc);
1856 state.pc = 0x0038;
1857 return elapsed_cycles + 13;
1858
1859 }
1860
1861 case Z80_INTERRUPT_MODE_2:
1862 default: {
1863
1864 int elapsed_cycles, vector;
1865
1866 elapsed_cycles = 0;
1867 SP -= 2;
1868 Z80_WRITE_WORD_INTERRUPT(SP, state.pc);
1869 vector = state.i << 8 | data_on_bus;
1870
1871#ifdef Z80_MASK_IM2_VECTOR_ADDRESS
1872
1873 vector &= 0xfffe;
1874
1875#endif
1876
1877 Z80_READ_WORD_INTERRUPT(vector, state.pc);
1878 return elapsed_cycles + 19;
1879
1880 }
1881
1882 }
1883
1884 } else
1885
1886 return 0;
1887}
1888
1889
1890int Z80::NMI()
1891{
1892 int elapsed_cycles;
1893
1894 state.status = 0;
1895
1896 state.iff2 = state.iff1;
1897 state.iff1 = 0;
1898 state.r = (state.r & 0x80) | ((state.r + 1) & 0x7f);
1899
1900 elapsed_cycles = 0;
1901 SP -= 2;
1902 Z80_WRITE_WORD_INTERRUPT(SP, state.pc);
1903 state.pc = 0x0066;
1904
1905 return elapsed_cycles + 11;
1906}
1907
1908
1909int Z80::step()
1910{
1911 state.status = 0;
1912 int elapsed_cycles = 0;
1913 int pc = state.pc;
1914 int opcode;
1915 Z80_FETCH_BYTE(pc, opcode);
1916 state.pc = pc + 1;
1917
1918 return intemulate(opcode, elapsed_cycles);
1919}
1920
1921
1922/* Actual emulation function. opcode is the first opcode to emulate, this is
1923 * needed by Z80Interrupt() for interrupt mode 0.
1924 */
1925
1926int Z80::intemulate(int opcode, int elapsed_cycles)
1927{
1928 int pc = state.pc;
1929 int r = state.r & 0x7f;
1930
1931 void * * registers = state.register_table;
1932
1933 int instruction = INSTRUCTION_TABLE[opcode];
1934
1935 bool repeatLoop;
1936
1937 do {
1938
1939 repeatLoop = false;
1940
1941 elapsed_cycles += 4;
1942 r++;
1943 switch (instruction) {
1944
1945 /* 8-bit load group. */
1946
1947 case LD_R_R: {
1948
1949 R(Y(opcode)) = R(Z(opcode));
1950 break;
1951
1952 }
1953
1954 case LD_R_N: {
1955
1956 READ_N(R(Y(opcode)));
1957 break;
1958
1959 }
1960
1961 case LD_R_INDIRECT_HL: {
1962
1963 if (registers == state.register_table) {
1964
1965 READ_BYTE(HL, R(Y(opcode)));
1966
1967 } else {
1968
1969 int d;
1970
1971 READ_D(d);
1972 d += HL_IX_IY;
1973 READ_BYTE(d, S(Y(opcode)));
1974
1975 elapsed_cycles += 5;
1976
1977 }
1978 break;
1979
1980 }
1981
1982 case LD_INDIRECT_HL_R: {
1983
1984 if (registers == state.register_table) {
1985
1986 WRITE_BYTE(HL, R(Z(opcode)));
1987
1988 } else {
1989
1990 int d;
1991
1992 READ_D(d);
1993 d += HL_IX_IY;
1994 WRITE_BYTE(d, S(Z(opcode)));
1995
1996 elapsed_cycles += 5;
1997
1998 }
1999 break;
2000
2001 }
2002
2003 case LD_INDIRECT_HL_N: {
2004
2005 int n;
2006
2007 if (registers == state.register_table) {
2008
2009 READ_N(n);
2010 WRITE_BYTE(HL, n);
2011
2012 } else {
2013
2014 int d;
2015
2016 READ_D(d);
2017 d += HL_IX_IY;
2018 READ_N(n);
2019 WRITE_BYTE(d, n);
2020
2021 elapsed_cycles += 2;
2022
2023 }
2024
2025 break;
2026
2027 }
2028
2029 case LD_A_INDIRECT_BC: {
2030
2031 READ_BYTE(BC, A);
2032 break;
2033
2034 }
2035
2036 case LD_A_INDIRECT_DE: {
2037
2038 READ_BYTE(DE, A);
2039 break;
2040
2041 }
2042
2043 case LD_A_INDIRECT_NN: {
2044
2045 int nn;
2046
2047 READ_NN(nn);
2048 READ_BYTE(nn, A);
2049 break;
2050
2051 }
2052
2053 case LD_INDIRECT_BC_A: {
2054
2055 WRITE_BYTE(BC, A);
2056 break;
2057
2058 }
2059
2060 case LD_INDIRECT_DE_A: {
2061
2062 WRITE_BYTE(DE, A);
2063 break;
2064
2065 }
2066
2067 case LD_INDIRECT_NN_A: {
2068
2069 int nn;
2070
2071 READ_NN(nn);
2072 WRITE_BYTE(nn, A);
2073 break;
2074
2075 }
2076
2077 case LD_A_I_LD_A_R: {
2078
2079 int a, f;
2080
2081 a = opcode == OPCODE_LD_A_I
2082 ? state.i
2083 : (state.r & 0x80) | (r & 0x7f);
2084 f = SZYX_FLAGS_TABLE[a];
2085
2086 /* Note: On a real processor, if an interrupt
2087 * occurs during the execution of either
2088 * "LD A, I" or "LD A, R", the parity flag is
2089 * reset. That can never happen here.
2090 */
2091
2092 f |= state.iff2 << Z80_P_FLAG_SHIFT;
2093 f |= F & Z80_C_FLAG;
2094
2095 AF = (a << 8) | f;
2096
2097 elapsed_cycles++;
2098
2099 break;
2100
2101 }
2102
2103 case LD_I_A_LD_R_A: {
2104
2105 if (opcode == OPCODE_LD_I_A)
2106
2107 state.i = A;
2108
2109 else {
2110
2111 state.r = A;
2112 r = A & 0x7f;
2113
2114 }
2115
2116 elapsed_cycles++;
2117
2118 break;
2119
2120 }
2121
2122 /* 16-bit load group. */
2123
2124 case LD_RR_NN: {
2125
2126 READ_NN(RR(P(opcode)));
2127 break;
2128
2129 }
2130
2131 case LD_HL_INDIRECT_NN: {
2132
2133 int nn;
2134
2135 READ_NN(nn);
2136 READ_WORD(nn, HL_IX_IY);
2137 break;
2138
2139 }
2140
2141 case LD_RR_INDIRECT_NN: {
2142
2143 int nn;
2144
2145 READ_NN(nn);
2146 READ_WORD(nn, RR(P(opcode)));
2147 break;
2148
2149 }
2150
2151 case LD_INDIRECT_NN_HL: {
2152
2153 int nn;
2154
2155 READ_NN(nn);
2156 WRITE_WORD(nn, HL_IX_IY);
2157 break;
2158
2159 }
2160
2161 case LD_INDIRECT_NN_RR: {
2162
2163 int nn;
2164
2165 READ_NN(nn);
2166 WRITE_WORD(nn, RR(P(opcode)));
2167 break;
2168
2169 }
2170
2171 case LD_SP_HL: {
2172
2173 SP = HL_IX_IY;
2174 elapsed_cycles += 2;
2175 break;
2176
2177 }
2178
2179 case PUSH_SS: {
2180
2181 PUSH(SS(P(opcode)));
2182 elapsed_cycles++;
2183 break;
2184
2185 }
2186
2187 case POP_SS: {
2188
2189 POP(SS(P(opcode)));
2190 break;
2191
2192 }
2193
2194 /* Exchange, block transfer and search group. */
2195
2196 case EX_DE_HL: {
2197
2198 EXCHANGE(DE, HL);
2199 break;
2200
2201 }
2202
2203 case EX_AF_AF_PRIME: {
2204
2205 EXCHANGE(AF, state.alternates[Z80_AF]);
2206 break;
2207
2208 }
2209
2210 case EXX: {
2211
2212 EXCHANGE(BC, state.alternates[Z80_BC]);
2213 EXCHANGE(DE, state.alternates[Z80_DE]);
2214 EXCHANGE(HL, state.alternates[Z80_HL]);
2215 break;
2216
2217 }
2218
2219 case EX_INDIRECT_SP_HL: {
2220
2221 int t;
2222
2223 READ_WORD(SP, t);
2224 WRITE_WORD(SP, HL_IX_IY);
2225 HL_IX_IY = t;
2226
2227 elapsed_cycles += 3;
2228
2229 break;
2230 }
2231
2232 case LDI_LDD: {
2233
2234 int n, f, d;
2235
2236 READ_BYTE(HL, n);
2237 WRITE_BYTE(DE, n);
2238
2239 f = F & SZC_FLAGS;
2240 f |= --BC ? Z80_P_FLAG : 0;
2241
2242 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
2243
2244 n += A;
2245 f |= n & Z80_X_FLAG;
2246 f |= (n << (Z80_Y_FLAG_SHIFT - 1))
2247 & Z80_Y_FLAG;
2248
2249 #endif
2250
2251 F = f;
2252
2253 d = opcode == OPCODE_LDI ? +1 : -1;
2254 DE += d;
2255 HL += d;
2256
2257 elapsed_cycles += 2;
2258
2259 break;
2260
2261 }
2262
2263 case LDIR_LDDR: {
2264
2265 int d, f, bc, de, hl, n;
2266
2267 #ifdef Z80_HANDLE_SELF_MODIFYING_CODE
2268
2269 int p, q;
2270
2271 p = (pc - 2) & 0xffff;
2272 q = (pc - 1) & 0xffff;
2273
2274 #endif
2275
2276 d = opcode == OPCODE_LDIR ? +1 : -1;
2277
2278 f = F & SZC_FLAGS;
2279 bc = BC;
2280 de = DE;
2281 hl = HL;
2282
2283 r -= 2;
2284 elapsed_cycles -= 8;
2285 for ( ; ; ) {
2286
2287 r += 2;
2288
2289 Z80_READ_BYTE(hl, n);
2290 Z80_WRITE_BYTE(de, n);
2291
2292 hl += d;
2293 de += d;
2294
2295 if (--bc)
2296
2297 elapsed_cycles += 21;
2298
2299 else {
2300
2301 elapsed_cycles += 16;
2302 break;
2303
2304 }
2305
2306 #ifdef Z80_HANDLE_SELF_MODIFYING_CODE
2307
2308 if (((de - d) & 0xffff) == p
2309 || ((de - d) & 0xffff) == q) {
2310
2311 f |= Z80_P_FLAG;
2312 pc -= 2;
2313 break;
2314
2315 }
2316
2317 #endif
2318
2319 f |= Z80_P_FLAG;
2320 pc -= 2;
2321 break;
2322
2323 }
2324
2325 HL = hl;
2326 DE = de;
2327 BC = bc;
2328
2329 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
2330
2331 n += A;
2332 f |= n & Z80_X_FLAG;
2333 f |= (n << (Z80_Y_FLAG_SHIFT - 1))
2334 & Z80_Y_FLAG;
2335
2336 #endif
2337
2338 F = f;
2339
2340 break;
2341
2342 }
2343
2344 case CPI_CPD: {
2345
2346 int a, n, z, f;
2347
2348 a = A;
2349 READ_BYTE(HL, n);
2350 z = a - n;
2351
2352 HL += opcode == OPCODE_CPI ? +1 : -1;
2353
2354 f = (a ^ n ^ z) & Z80_H_FLAG;
2355
2356 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
2357
2358 n = z - (f >> Z80_H_FLAG_SHIFT);
2359 f |= (n << (Z80_Y_FLAG_SHIFT - 1))
2360 & Z80_Y_FLAG;
2361 f |= n & Z80_X_FLAG;
2362
2363 #endif
2364
2365 f |= SZYX_FLAGS_TABLE[z & 0xff] & SZ_FLAGS;
2366 f |= --BC ? Z80_P_FLAG : 0;
2367 F = f | Z80_N_FLAG | (F & Z80_C_FLAG);
2368
2369 elapsed_cycles += 5;
2370
2371 break;
2372
2373 }
2374
2375 case CPIR_CPDR: {
2376
2377 int d, a, bc, hl, n, z, f;
2378
2379 d = opcode == OPCODE_CPIR ? +1 : -1;
2380
2381 a = A;
2382 bc = BC;
2383 hl = HL;
2384
2385 r -= 2;
2386 elapsed_cycles -= 8;
2387 for ( ; ; ) {
2388
2389 r += 2;
2390
2391 Z80_READ_BYTE(hl, n);
2392 z = a - n;
2393
2394 hl += d;
2395 if (--bc && z)
2396
2397 elapsed_cycles += 21;
2398
2399 else {
2400
2401 elapsed_cycles += 16;
2402 break;
2403
2404 }
2405
2406 pc -= 2;
2407 break;
2408
2409 }
2410
2411 HL = hl;
2412 BC = bc;
2413
2414 f = (a ^ n ^ z) & Z80_H_FLAG;
2415
2416 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
2417
2418 n = z - (f >> Z80_H_FLAG_SHIFT);
2419 f |= (n << (Z80_Y_FLAG_SHIFT - 1))
2420 & Z80_Y_FLAG;
2421 f |= n & Z80_X_FLAG;
2422
2423 #endif
2424
2425 f |= SZYX_FLAGS_TABLE[z & 0xff] & SZ_FLAGS;
2426 f |= bc ? Z80_P_FLAG : 0;
2427 F = f | Z80_N_FLAG | (F & Z80_C_FLAG);
2428
2429 break;
2430
2431 }
2432
2433 /* 8-bit arithmetic and logical group. */
2434
2435 case ADD_R: {
2436
2437 ADD(R(Z(opcode)));
2438 break;
2439
2440 }
2441
2442 case ADD_N: {
2443
2444 int n;
2445
2446 READ_N(n);
2447 ADD(n);
2448 break;
2449
2450 }
2451
2452 case ADD_INDIRECT_HL: {
2453
2454 int x;
2455
2456 READ_INDIRECT_HL(x);
2457 ADD(x);
2458 break;
2459
2460 }
2461
2462 case ADC_R: {
2463
2464 ADC(R(Z(opcode)));
2465 break;
2466
2467 }
2468
2469 case ADC_N: {
2470
2471 int n;
2472
2473 READ_N(n);
2474 ADC(n);
2475 break;
2476
2477 }
2478
2479 case ADC_INDIRECT_HL: {
2480
2481 int x;
2482
2483 READ_INDIRECT_HL(x);
2484 ADC(x);
2485 break;
2486
2487 }
2488
2489 case SUB_R: {
2490
2491 SUB(R(Z(opcode)));
2492 break;
2493
2494 }
2495
2496 case SUB_N: {
2497
2498 int n;
2499
2500 READ_N(n);
2501 SUB(n);
2502 break;
2503
2504 }
2505
2506 case SUB_INDIRECT_HL: {
2507
2508 int x;
2509
2510 READ_INDIRECT_HL(x);
2511 SUB(x);
2512 break;
2513
2514 }
2515
2516 case SBC_R: {
2517
2518 SBC(R(Z(opcode)));
2519 break;
2520
2521 }
2522
2523 case SBC_N: {
2524
2525 int n;
2526
2527 READ_N(n);
2528 SBC(n);
2529 break;
2530
2531 }
2532
2533 case SBC_INDIRECT_HL: {
2534
2535 int x;
2536
2537 READ_INDIRECT_HL(x);
2538 SBC(x);
2539 break;
2540
2541 }
2542
2543 case AND_R: {
2544
2545 AND(R(Z(opcode)));
2546 break;
2547
2548 }
2549
2550 case AND_N: {
2551
2552 int n;
2553
2554 READ_N(n);
2555 AND(n);
2556 break;
2557
2558 }
2559
2560 case AND_INDIRECT_HL: {
2561
2562 int x;
2563
2564 READ_INDIRECT_HL(x);
2565 AND(x);
2566 break;
2567
2568 }
2569
2570 case OR_R: {
2571
2572 OR(R(Z(opcode)));
2573 break;
2574
2575 }
2576
2577 case OR_N: {
2578
2579 int n;
2580
2581 READ_N(n);
2582 OR(n);
2583 break;
2584
2585 }
2586
2587 case OR_INDIRECT_HL: {
2588
2589 int x;
2590
2591 READ_INDIRECT_HL(x);
2592 OR(x);
2593 break;
2594
2595 }
2596
2597 case XOR_R: {
2598
2599 XOR(R(Z(opcode)));
2600 break;
2601
2602 }
2603
2604 case XOR_N: {
2605
2606 int n;
2607
2608 READ_N(n);
2609 XOR(n);
2610 break;
2611
2612 }
2613
2614 case XOR_INDIRECT_HL: {
2615
2616 int x;
2617
2618 READ_INDIRECT_HL(x);
2619 XOR(x);
2620 break;
2621
2622 }
2623
2624 case CP_R: {
2625
2626 CP(R(Z(opcode)));
2627 break;
2628
2629 }
2630
2631 case CP_N: {
2632
2633 int n;
2634
2635 READ_N(n);
2636 CP(n);
2637 break;
2638
2639 }
2640
2641 case CP_INDIRECT_HL: {
2642
2643 int x;
2644
2645 READ_INDIRECT_HL(x);
2646 CP(x);
2647 break;
2648
2649 }
2650
2651 case INC_R: {
2652
2653 INC(R(Y(opcode)));
2654 break;
2655
2656 }
2657
2658 case INC_INDIRECT_HL: {
2659
2660 int x;
2661
2662 if (registers == state.register_table) {
2663
2664 READ_BYTE(HL, x);
2665 INC(x);
2666 WRITE_BYTE(HL, x);
2667
2668 elapsed_cycles++;
2669
2670 } else {
2671
2672 int d;
2673
2674 READ_D(d);
2675 d += HL_IX_IY;
2676 READ_BYTE(d, x);
2677 INC(x);
2678 WRITE_BYTE(d, x);
2679
2680 elapsed_cycles += 6;
2681
2682 }
2683 break;
2684
2685 }
2686
2687 case DEC_R: {
2688
2689 DEC(R(Y(opcode)));
2690 break;
2691
2692 }
2693
2694 case DEC_INDIRECT_HL: {
2695
2696 int x;
2697
2698 if (registers == state.register_table) {
2699
2700 READ_BYTE(HL, x);
2701 DEC(x);
2702 WRITE_BYTE(HL, x);
2703
2704 elapsed_cycles++;
2705
2706 } else {
2707
2708 int d;
2709
2710 READ_D(d);
2711 d += HL_IX_IY;
2712 READ_BYTE(d, x);
2713 DEC(x);
2714 WRITE_BYTE(d, x);
2715
2716 elapsed_cycles += 6;
2717
2718 }
2719 break;
2720
2721 }
2722
2723 /* General-purpose arithmetic and CPU control group. */
2724
2725 case DAA: {
2726
2727 int a, c, d;
2728
2729 /* The following algorithm is from
2730 * comp.sys.sinclair's FAQ.
2731 */
2732
2733 a = A;
2734 if (a > 0x99 || (F & Z80_C_FLAG)) {
2735
2736 c = Z80_C_FLAG;
2737 d = 0x60;
2738
2739 } else
2740
2741 c = d = 0;
2742
2743 if ((a & 0x0f) > 0x09 || (F & Z80_H_FLAG))
2744
2745 d += 0x06;
2746
2747 A += F & Z80_N_FLAG ? -d : +d;
2748 F = SZYXP_FLAGS_TABLE[A]
2749 | ((A ^ a) & Z80_H_FLAG)
2750 | (F & Z80_N_FLAG)
2751 | c;
2752
2753 break;
2754
2755 }
2756
2757 case CPL: {
2758
2759 A = ~A;
2760 F = (F & (SZPV_FLAGS | Z80_C_FLAG))
2761
2762 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
2763
2764 | (A & YX_FLAGS)
2765
2766 #endif
2767
2768 | Z80_H_FLAG | Z80_N_FLAG;
2769
2770 break;
2771
2772 }
2773
2774 case NEG: {
2775
2776 int a, f, z, c;
2777
2778 a = A;
2779 z = -a;
2780
2781 c = a ^ z;
2782 f = Z80_N_FLAG | (c & Z80_H_FLAG);
2783 f |= SZYX_FLAGS_TABLE[z &= 0xff];
2784 c &= 0x0180;
2785 f |= OVERFLOW_TABLE[c >> 7];
2786 f |= c >> (8 - Z80_C_FLAG_SHIFT);
2787
2788 A = z;
2789 F = f;
2790
2791 break;
2792
2793 }
2794
2795 case CCF: {
2796
2797 int c;
2798
2799 c = F & Z80_C_FLAG;
2800 F = (F & SZPV_FLAGS)
2801 | (c << Z80_H_FLAG_SHIFT)
2802
2803 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
2804
2805 | (A & YX_FLAGS)
2806
2807 #endif
2808
2809 | (c ^ Z80_C_FLAG);
2810
2811 break;
2812
2813 }
2814
2815 case SCF: {
2816
2817 F = (F & SZPV_FLAGS)
2818
2819 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
2820
2821 | (A & YX_FLAGS)
2822
2823 #endif
2824
2825 | Z80_C_FLAG;
2826
2827 break;
2828
2829 }
2830
2831 case NOP: {
2832
2833 break;
2834
2835 }
2836
2837 case HALT: {
2838
2839 #ifdef Z80_CATCH_HALT
2840
2841 state.status = Z80_STATUS_HALT;
2842
2843 #endif
2844
2845 break;
2846
2847 }
2848
2849 case DI: {
2850
2851 state.iff1 = state.iff2 = 0;
2852
2853 #ifdef Z80_CATCH_DI
2854
2855 state.status = Z80_STATUS_DI;
2856
2857 #endif
2858
2859 break;
2860
2861 }
2862
2863 case EI: {
2864
2865 state.iff1 = state.iff2 = 1;
2866
2867 #ifdef Z80_CATCH_EI
2868
2869 state.status = Z80_STATUS_EI;
2870
2871 #endif
2872
2873 break;
2874
2875 }
2876
2877 case IM_N: {
2878
2879 /* "IM 0/1" (0xed prefixed opcodes 0x4e and
2880 * 0x6e) is treated like a "IM 0".
2881 */
2882
2883 if ((Y(opcode) & 0x03) <= 0x01)
2884
2885 state.im = Z80_INTERRUPT_MODE_0;
2886
2887 else if (!(Y(opcode) & 1))
2888
2889 state.im = Z80_INTERRUPT_MODE_1;
2890
2891 else
2892
2893 state.im = Z80_INTERRUPT_MODE_2;
2894
2895 break;
2896
2897 }
2898
2899 /* 16-bit arithmetic group. */
2900
2901 case ADD_HL_RR: {
2902
2903 int x, y, z, f, c;
2904
2905 x = HL_IX_IY;
2906 y = RR(P(opcode));
2907 z = x + y;
2908
2909 c = x ^ y ^ z;
2910 f = F & SZPV_FLAGS;
2911
2912 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
2913
2914 f |= (z >> 8) & YX_FLAGS;
2915 f |= (c >> 8) & Z80_H_FLAG;
2916
2917 #endif
2918
2919 f |= c >> (16 - Z80_C_FLAG_SHIFT);
2920
2921 HL_IX_IY = z;
2922 F = f;
2923
2924 elapsed_cycles += 7;
2925
2926 break;
2927
2928 }
2929
2930 case ADC_HL_RR: {
2931
2932 int x, y, z, f, c;
2933
2934 x = HL;
2935 y = RR(P(opcode));
2936 z = x + y + (F & Z80_C_FLAG);
2937
2938 c = x ^ y ^ z;
2939 f = z & 0xffff
2940 ? (z >> 8) & SYX_FLAGS
2941 : Z80_Z_FLAG;
2942
2943 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
2944
2945 f |= (c >> 8) & Z80_H_FLAG;
2946
2947 #endif
2948
2949 f |= OVERFLOW_TABLE[c >> 15];
2950 f |= z >> (16 - Z80_C_FLAG_SHIFT);
2951
2952 HL = z;
2953 F = f;
2954
2955 elapsed_cycles += 7;
2956
2957 break;
2958
2959 }
2960
2961 case SBC_HL_RR: {
2962
2963 int x, y, z, f, c;
2964
2965 x = HL;
2966 y = RR(P(opcode));
2967 z = x - y - (F & Z80_C_FLAG);
2968
2969 c = x ^ y ^ z;
2970 f = Z80_N_FLAG;
2971 f |= z & 0xffff
2972 ? (z >> 8) & SYX_FLAGS
2973 : Z80_Z_FLAG;
2974
2975 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
2976
2977 f |= (c >> 8) & Z80_H_FLAG;
2978
2979 #endif
2980
2981 c &= 0x018000;
2982 f |= OVERFLOW_TABLE[c >> 15];
2983 f |= c >> (16 - Z80_C_FLAG_SHIFT);
2984
2985 HL = z;
2986 F = f;
2987
2988 elapsed_cycles += 7;
2989
2990 break;
2991
2992 }
2993
2994 case INC_RR: {
2995
2996 int x;
2997
2998 x = RR(P(opcode));
2999 x++;
3000 RR(P(opcode)) = x;
3001
3002 elapsed_cycles += 2;
3003
3004 break;
3005
3006 }
3007
3008 case DEC_RR: {
3009
3010 int x;
3011
3012 x = RR(P(opcode));
3013 x--;
3014 RR(P(opcode)) = x;
3015
3016 elapsed_cycles += 2;
3017
3018 break;
3019
3020 }
3021
3022 /* Rotate and shift group. */
3023
3024 case RLCA: {
3025
3026 A = (A << 1) | (A >> 7);
3027 F = (F & SZPV_FLAGS)
3028 | (A & (YX_FLAGS | Z80_C_FLAG));
3029 break;
3030
3031 }
3032
3033 case RLA: {
3034
3035 int a, f;
3036
3037 a = A << 1;
3038 f = (F & SZPV_FLAGS)
3039
3040 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
3041
3042 | (a & YX_FLAGS)
3043
3044 #endif
3045
3046 | (A >> 7);
3047 A = a | (F & Z80_C_FLAG);
3048 F = f;
3049
3050 break;
3051
3052 }
3053
3054 case RRCA: {
3055
3056 int c;
3057
3058 c = A & 0x01;
3059 A = (A >> 1) | (A << 7);
3060 F = (F & SZPV_FLAGS)
3061
3062 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
3063
3064 | (A & YX_FLAGS)
3065
3066 #endif
3067
3068 | c;
3069
3070 break;
3071
3072 }
3073
3074 case RRA: {
3075
3076 int c;
3077
3078 c = A & 0x01;
3079 A = (A >> 1) | ((F & Z80_C_FLAG) << 7);
3080 F = (F & SZPV_FLAGS)
3081
3082 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
3083
3084 | (A & YX_FLAGS)
3085
3086 #endif
3087
3088 | c;
3089
3090 break;
3091
3092 }
3093
3094 case RLC_R: {
3095
3096 RLC(R(Z(opcode)));
3097 break;
3098
3099 }
3100
3101 case RLC_INDIRECT_HL: {
3102
3103 int x;
3104
3105 if (registers == state.register_table) {
3106
3107 READ_BYTE(HL, x);
3108 RLC(x);
3109 WRITE_BYTE(HL, x);
3110
3111 elapsed_cycles++;
3112
3113 } else {
3114
3115 int d;
3116
3117 Z80_FETCH_BYTE(pc, d);
3118 d = ((signed char) d) + HL_IX_IY;
3119
3120 READ_BYTE(d, x);
3121 RLC(x);
3122 WRITE_BYTE(d, x);
3123
3124 if (Z(opcode) != INDIRECT_HL)
3125
3126 R(Z(opcode)) = x;
3127
3128 pc += 2;
3129
3130 elapsed_cycles += 5;
3131
3132 }
3133
3134 break;
3135
3136 }
3137
3138 case RL_R: {
3139
3140 RL(R(Z(opcode)));
3141 break;
3142
3143 }
3144
3145 case RL_INDIRECT_HL: {
3146
3147 int x;
3148
3149 if (registers == state.register_table) {
3150
3151 READ_BYTE(HL, x);
3152 RL(x);
3153 WRITE_BYTE(HL, x);
3154
3155 elapsed_cycles++;
3156
3157 } else {
3158
3159 int d;
3160
3161 Z80_FETCH_BYTE(pc, d);
3162 d = ((signed char) d) + HL_IX_IY;
3163
3164 READ_BYTE(d, x);
3165 RL(x);
3166 WRITE_BYTE(d, x);
3167
3168 if (Z(opcode) != INDIRECT_HL)
3169
3170 R(Z(opcode)) = x;
3171
3172 pc += 2;
3173
3174 elapsed_cycles += 5;
3175
3176 }
3177 break;
3178
3179 }
3180
3181 case RRC_R: {
3182
3183 RRC(R(Z(opcode)));
3184 break;
3185
3186 }
3187
3188 case RRC_INDIRECT_HL: {
3189
3190 int x;
3191
3192 if (registers == state.register_table) {
3193
3194 READ_BYTE(HL, x);
3195 RRC(x);
3196 WRITE_BYTE(HL, x);
3197
3198 elapsed_cycles++;
3199
3200 } else {
3201
3202 int d;
3203
3204 Z80_FETCH_BYTE(pc, d);
3205 d = ((signed char) d) + HL_IX_IY;
3206
3207 READ_BYTE(d, x);
3208 RRC(x);
3209 WRITE_BYTE(d, x);
3210
3211 if (Z(opcode) != INDIRECT_HL)
3212
3213 R(Z(opcode)) = x;
3214
3215 pc += 2;
3216
3217 elapsed_cycles += 5;
3218
3219 }
3220 break;
3221
3222 }
3223
3224 case RR_R: {
3225
3226 RR_INSTRUCTION(R(Z(opcode)));
3227 break;
3228
3229 }
3230
3231 case RR_INDIRECT_HL: {
3232
3233 int x;
3234
3235 if (registers == state.register_table) {
3236
3237 READ_BYTE(HL, x);
3238 RR_INSTRUCTION(x);
3239 WRITE_BYTE(HL, x);
3240
3241 elapsed_cycles++;
3242
3243 } else {
3244
3245 int d;
3246
3247 Z80_FETCH_BYTE(pc, d);
3248 d = ((signed char) d) + HL_IX_IY;
3249
3250 READ_BYTE(d, x);
3251 RR_INSTRUCTION(x);
3252 WRITE_BYTE(d, x);
3253
3254 if (Z(opcode) != INDIRECT_HL)
3255
3256 R(Z(opcode)) = x;
3257
3258 pc += 2;
3259
3260 elapsed_cycles += 5;
3261
3262 }
3263 break;
3264
3265 }
3266
3267 case SLA_R: {
3268
3269 SLA(R(Z(opcode)));
3270 break;
3271
3272 }
3273
3274 case SLA_INDIRECT_HL: {
3275
3276 int x;
3277
3278 if (registers == state.register_table) {
3279
3280 READ_BYTE(HL, x);
3281 SLA(x);
3282 WRITE_BYTE(HL, x);
3283
3284 elapsed_cycles++;
3285
3286 } else {
3287
3288 int d;
3289
3290 Z80_FETCH_BYTE(pc, d);
3291 d = ((signed char) d) + HL_IX_IY;
3292
3293 READ_BYTE(d, x);
3294 SLA(x);
3295 WRITE_BYTE(d, x);
3296
3297 if (Z(opcode) != INDIRECT_HL)
3298
3299 R(Z(opcode)) = x;
3300
3301 pc += 2;
3302
3303 elapsed_cycles += 5;
3304
3305 }
3306 break;
3307
3308 }
3309
3310 case SLL_R: {
3311
3312 SLL(R(Z(opcode)));
3313 break;
3314
3315 }
3316
3317 case SLL_INDIRECT_HL: {
3318
3319 int x;
3320
3321 if (registers == state.register_table) {
3322
3323 READ_BYTE(HL, x);
3324 SLL(x);
3325 WRITE_BYTE(HL, x);
3326
3327 elapsed_cycles++;
3328
3329 } else {
3330
3331 int d;
3332
3333 Z80_FETCH_BYTE(pc, d);
3334 d = ((signed char) d) + HL_IX_IY;
3335
3336 READ_BYTE(d, x);
3337 SLL(x);
3338 WRITE_BYTE(d, x);
3339
3340 if (Z(opcode) != INDIRECT_HL)
3341
3342 R(Z(opcode)) = x;
3343
3344 pc += 2;
3345
3346 elapsed_cycles += 5;
3347
3348 }
3349 break;
3350
3351 }
3352
3353 case SRA_R: {
3354
3355 SRA(R(Z(opcode)));
3356 break;
3357
3358 }
3359
3360 case SRA_INDIRECT_HL: {
3361
3362 int x;
3363
3364 if (registers == state.register_table) {
3365
3366 READ_BYTE(HL, x);
3367 SRA(x);
3368 WRITE_BYTE(HL, x);
3369
3370 elapsed_cycles++;
3371
3372 } else {
3373
3374 int d;
3375
3376 Z80_FETCH_BYTE(pc, d);
3377 d = ((signed char) d) + HL_IX_IY;
3378
3379 READ_BYTE(d, x);
3380 SRA(x);
3381 WRITE_BYTE(d, x);
3382
3383 if (Z(opcode) != INDIRECT_HL)
3384
3385 R(Z(opcode)) = x;
3386
3387 pc += 2;
3388
3389 elapsed_cycles += 5;
3390
3391 }
3392 break;
3393
3394 }
3395
3396 case SRL_R: {
3397
3398 SRL(R(Z(opcode)));
3399 break;
3400
3401 }
3402
3403 case SRL_INDIRECT_HL: {
3404
3405 int x;
3406
3407 if (registers == state.register_table) {
3408
3409 READ_BYTE(HL, x);
3410 SRL(x);
3411 WRITE_BYTE(HL, x);
3412
3413 elapsed_cycles++;
3414
3415 } else {
3416
3417 int d;
3418
3419 Z80_FETCH_BYTE(pc, d);
3420 d = ((signed char) d) + HL_IX_IY;
3421
3422 READ_BYTE(d, x);
3423 SRL(x);
3424 WRITE_BYTE(d, x);
3425
3426 if (Z(opcode) != INDIRECT_HL)
3427
3428 R(Z(opcode)) = x;
3429
3430 pc += 2;
3431
3432 elapsed_cycles += 5;
3433
3434 }
3435 break;
3436
3437 }
3438
3439 case RLD_RRD: {
3440
3441 int x, y;
3442
3443 READ_BYTE(HL, x);
3444 y = (A & 0xf0) << 8;
3445 y |= opcode == OPCODE_RLD
3446 ? (x << 4) | (A & 0x0f)
3447 : ((x & 0x0f) << 8)
3448 | ((A & 0x0f) << 4)
3449 | (x >> 4);
3450 WRITE_BYTE(HL, y);
3451 y >>= 8;
3452
3453 A = y;
3454 F = SZYXP_FLAGS_TABLE[y] | (F & Z80_C_FLAG);
3455
3456 elapsed_cycles += 4;
3457
3458 break;
3459
3460 }
3461
3462 /* Bit set, reset, and test group. */
3463
3464 case BIT_B_R: {
3465
3466 int x;
3467
3468 x = R(Z(opcode)) & (1 << Y(opcode));
3469 F = (x ? 0 : Z80_Z_FLAG | Z80_P_FLAG)
3470
3471 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
3472
3473 | (x & Z80_S_FLAG)
3474 | (R(Z(opcode)) & YX_FLAGS)
3475
3476 #endif
3477
3478 | Z80_H_FLAG
3479 | (F & Z80_C_FLAG);
3480
3481 break;
3482
3483 }
3484
3485 case BIT_B_INDIRECT_HL: {
3486
3487 int d, x;
3488
3489 if (registers == state.register_table) {
3490
3491 d = HL;
3492
3493 elapsed_cycles++;
3494
3495 } else {
3496
3497 Z80_FETCH_BYTE(pc, d);
3498 d = ((signed char) d) + HL_IX_IY;
3499
3500 pc += 2;
3501
3502 elapsed_cycles += 5;
3503
3504 }
3505
3506 READ_BYTE(d, x);
3507 x &= 1 << Y(opcode);
3508 F = (x ? 0 : Z80_Z_FLAG | Z80_P_FLAG)
3509
3510 #ifndef Z80_DOCUMENTED_FLAGS_ONLY
3511
3512 | (x & Z80_S_FLAG)
3513 | (d & YX_FLAGS)
3514
3515 #endif
3516
3517 | Z80_H_FLAG
3518 | (F & Z80_C_FLAG);
3519
3520 break;
3521
3522 }
3523
3524 case SET_B_R: {
3525
3526 R(Z(opcode)) |= 1 << Y(opcode);
3527 break;
3528
3529 }
3530
3531 case SET_B_INDIRECT_HL: {
3532
3533 int x;
3534
3535 if (registers == state.register_table) {
3536
3537 READ_BYTE(HL, x);
3538 x |= 1 << Y(opcode);
3539 WRITE_BYTE(HL, x);
3540
3541 elapsed_cycles++;
3542
3543 } else {
3544
3545 int d;
3546
3547 Z80_FETCH_BYTE(pc, d);
3548 d = ((signed char) d) + HL_IX_IY;
3549
3550 READ_BYTE(d, x);
3551 x |= 1 << Y(opcode);
3552 WRITE_BYTE(d, x);
3553
3554 if (Z(opcode) != INDIRECT_HL)
3555
3556 R(Z(opcode)) = x;
3557
3558 pc += 2;
3559
3560 elapsed_cycles += 5;
3561
3562 }
3563 break;
3564
3565 }
3566
3567 case RES_B_R: {
3568
3569 R(Z(opcode)) &= ~(1 << Y(opcode));
3570 break;
3571
3572 }
3573
3574 case RES_B_INDIRECT_HL: {
3575
3576 int x;
3577
3578 if (registers == state.register_table) {
3579
3580 READ_BYTE(HL, x);
3581 x &= ~(1 << Y(opcode));
3582 WRITE_BYTE(HL, x);
3583
3584 elapsed_cycles++;
3585
3586 } else {
3587
3588 int d;
3589
3590 Z80_FETCH_BYTE(pc, d);
3591 d = ((signed char) d) + HL_IX_IY;
3592
3593 READ_BYTE(d, x);
3594 x &= ~(1 << Y(opcode));
3595 WRITE_BYTE(d, x);
3596
3597 if (Z(opcode) != INDIRECT_HL)
3598
3599 R(Z(opcode)) = x;
3600
3601 pc += 2;
3602
3603 elapsed_cycles += 5;
3604
3605 }
3606 break;
3607
3608 }
3609
3610 /* Jump group. */
3611
3612 case JP_NN: {
3613
3614 int nn;
3615
3616 Z80_FETCH_WORD(pc, nn);
3617 pc = nn;
3618
3619 elapsed_cycles += 6;
3620
3621 break;
3622
3623 }
3624
3625 case JP_CC_NN: {
3626
3627 int nn;
3628
3629 if (CC(Y(opcode))) {
3630
3631 Z80_FETCH_WORD(pc, nn);
3632 pc = nn;
3633
3634 } else {
3635
3636 #ifdef Z80_FALSE_CONDITION_FETCH
3637
3638 Z80_FETCH_WORD(pc, nn);
3639
3640 #endif
3641
3642 pc += 2;
3643
3644 }
3645
3646 elapsed_cycles += 6;
3647
3648 break;
3649
3650 }
3651
3652 case JR_E: {
3653
3654 int e;
3655
3656 Z80_FETCH_BYTE(pc, e);
3657 pc += ((signed char) e) + 1;
3658
3659 elapsed_cycles += 8;
3660
3661 break;
3662
3663 }
3664
3665 case JR_DD_E: {
3666
3667 int e;
3668
3669 if (DD(Q(opcode))) {
3670
3671 Z80_FETCH_BYTE(pc, e);
3672 pc += ((signed char) e) + 1;
3673
3674 elapsed_cycles += 8;
3675
3676 } else {
3677
3678 #ifdef Z80_FALSE_CONDITION_FETCH
3679
3680 Z80_FETCH_BYTE(pc, e);
3681
3682 #endif
3683
3684 pc++;
3685
3686 elapsed_cycles += 3;
3687
3688 }
3689 break;
3690
3691 }
3692
3693 case JP_HL: {
3694
3695 pc = HL_IX_IY;
3696 break;
3697
3698 }
3699
3700 case DJNZ_E: {
3701
3702 int e;
3703
3704 if (--B) {
3705
3706 Z80_FETCH_BYTE(pc, e);
3707 pc += ((signed char) e) + 1;
3708
3709 elapsed_cycles += 9;
3710
3711 } else {
3712
3713 #ifdef Z80_FALSE_CONDITION_FETCH
3714
3715 Z80_FETCH_BYTE(pc, e);
3716
3717 #endif
3718
3719 pc++;
3720
3721 elapsed_cycles += 4;
3722
3723 }
3724 break;
3725
3726 }
3727
3728 /* Call and return group. */
3729
3730 case CALL_NN: {
3731
3732 int nn;
3733
3734 READ_NN(nn);
3735 PUSH(pc);
3736 pc = nn;
3737
3738 elapsed_cycles++;
3739
3740 break;
3741
3742 }
3743
3744 case CALL_CC_NN: {
3745
3746 int nn;
3747
3748 if (CC(Y(opcode))) {
3749
3750 READ_NN(nn);
3751 PUSH(pc);
3752 pc = nn;
3753
3754 elapsed_cycles++;
3755
3756 } else {
3757
3758 #ifdef Z80_FALSE_CONDITION_FETCH
3759
3760 Z80_FETCH_WORD(pc, nn);
3761
3762 #endif
3763
3764 pc += 2;
3765
3766 elapsed_cycles += 6;
3767
3768 }
3769 break;
3770
3771 }
3772
3773 case RET: {
3774
3775 POP(pc);
3776 break;
3777
3778 }
3779
3780 case RET_CC: {
3781
3782 if (CC(Y(opcode))) {
3783
3784 POP(pc);
3785
3786 }
3787 elapsed_cycles++;
3788 break;
3789
3790 }
3791
3792 case RETI_RETN: {
3793
3794 state.iff1 = state.iff2;
3795 POP(pc);
3796
3797 #if defined(Z80_CATCH_RETI) && defined(Z80_CATCH_RETN)
3798
3799 state.status = opcode == OPCODE_RETI
3800 ? Z80_STATUS_RETI
3801 : Z80_STATUS_RETN;
3802
3803 #elif defined(Z80_CATCH_RETI)
3804
3805 state.status = Z80_STATUS_RETI;
3806
3807 #elif defined(Z80_CATCH_RETN)
3808
3809 state.status = Z80_STATUS_RETN;
3810
3811 #endif
3812
3813 break;
3814
3815 }
3816
3817 case RST_P: {
3818
3819 PUSH(pc);
3820 pc = RST_TABLE[Y(opcode)];
3821 elapsed_cycles++;
3822 break;
3823
3824 }
3825
3826 /* Input and output group. */
3827
3828 case IN_A_N: {
3829
3830 int n;
3831
3832 READ_N(n);
3833 Z80_INPUT_BYTE(n, A);
3834
3835 elapsed_cycles += 4;
3836
3837 break;
3838
3839 }
3840
3841 case IN_R_C: {
3842
3843 int x;
3844 Z80_INPUT_BYTE(C, x);
3845 if (Y(opcode) != INDIRECT_HL)
3846
3847 R(Y(opcode)) = x;
3848
3849 F = SZYXP_FLAGS_TABLE[x] | (F & Z80_C_FLAG);
3850
3851 elapsed_cycles += 4;
3852
3853 break;
3854
3855 }
3856
3857 /* Some of the undocumented flags for "INI", "IND",
3858 * "INIR", "INDR", "OUTI", "OUTD", "OTIR", and
3859 * "OTDR" are really really strange. The emulator
3860 * implements the specifications described in "The
3861 * Undocumented Z80 Documented Version 0.91".
3862 */
3863
3864 case INI_IND: {
3865
3866 int x, f;
3867
3868 Z80_INPUT_BYTE(C, x);
3869 WRITE_BYTE(HL, x);
3870
3871 f = SZYX_FLAGS_TABLE[--B & 0xff]
3872 | (x >> (7 - Z80_N_FLAG_SHIFT));
3873 if (opcode == OPCODE_INI) {
3874
3875 HL++;
3876 x += (C + 1) & 0xff;
3877
3878 } else {
3879
3880 HL--;
3881 x += (C - 1) & 0xff;
3882
3883 }
3884 f |= x & 0x0100 ? HC_FLAGS : 0;
3885 f |= SZYXP_FLAGS_TABLE[(x & 0x07) ^ B]
3886 & Z80_P_FLAG;
3887 F = f;
3888
3889 elapsed_cycles += 5;
3890
3891 break;
3892
3893 }
3894
3895 case INIR_INDR: {
3896
3897 int d, b, hl, x, f;
3898
3899 #ifdef Z80_HANDLE_SELF_MODIFYING_CODE
3900
3901 int p, q;
3902
3903 p = (pc - 2) & 0xffff;
3904 q = (pc - 1) & 0xffff;
3905
3906 #endif
3907
3908 d = opcode == OPCODE_INIR ? +1 : -1;
3909
3910 b = B;
3911 hl = HL;
3912
3913 r -= 2;
3914 elapsed_cycles -= 8;
3915 for ( ; ; ) {
3916
3917 r += 2;
3918
3919 Z80_INPUT_BYTE(C, x);
3920 Z80_WRITE_BYTE(hl, x);
3921
3922 hl += d;
3923
3924 if (--b)
3925
3926 elapsed_cycles += 21;
3927
3928 else {
3929
3930 f = Z80_Z_FLAG;
3931 elapsed_cycles += 16;
3932 break;
3933
3934 }
3935
3936 #ifdef Z80_HANDLE_SELF_MODIFYING_CODE
3937
3938 if (((hl - d) & 0xffff) == p
3939 || ((hl - d) & 0xffff) == q) {
3940
3941 f = SZYX_FLAGS_TABLE[b];
3942 pc -= 2;
3943 break;
3944
3945 }
3946
3947 #endif
3948
3949 f = SZYX_FLAGS_TABLE[b];
3950 pc -= 2;
3951 break;
3952
3953 }
3954
3955 HL = hl;
3956 B = b;
3957
3958 f |= x >> (7 - Z80_N_FLAG_SHIFT);
3959 x += (C + d) & 0xff;
3960 f |= x & 0x0100 ? HC_FLAGS : 0;
3961 f |= SZYXP_FLAGS_TABLE[(x & 0x07) ^ b]
3962 & Z80_P_FLAG;
3963 F = f;
3964
3965 break;
3966
3967 }
3968
3969 case OUT_N_A: {
3970
3971 int n;
3972
3973 READ_N(n);
3974 Z80_OUTPUT_BYTE(n, A);
3975
3976 elapsed_cycles += 4;
3977
3978 break;
3979
3980 }
3981
3982 case OUT_C_R: {
3983
3984 int x;
3985
3986 x = Y(opcode) != INDIRECT_HL
3987 ? R(Y(opcode))
3988 : 0;
3989 Z80_OUTPUT_BYTE(C, x);
3990
3991 elapsed_cycles += 4;
3992
3993 break;
3994
3995 }
3996
3997 case OUTI_OUTD: {
3998
3999 int x, f;
4000
4001 READ_BYTE(HL, x);
4002 Z80_OUTPUT_BYTE(C, x);
4003
4004 HL += opcode == OPCODE_OUTI ? +1 : -1;
4005
4006 f = SZYX_FLAGS_TABLE[--B & 0xff]
4007 | (x >> (7 - Z80_N_FLAG_SHIFT));
4008 x += HL & 0xff;
4009 f |= x & 0x0100 ? HC_FLAGS : 0;
4010 f |= SZYXP_FLAGS_TABLE[(x & 0x07) ^ B]
4011 & Z80_P_FLAG;
4012 F = f;
4013
4014 break;
4015
4016 }
4017
4018 case OTIR_OTDR: {
4019
4020 int d, b, hl, x, f;
4021
4022 d = opcode == OPCODE_OTIR ? +1 : -1;
4023
4024 b = B;
4025 hl = HL;
4026
4027 r -= 2;
4028 elapsed_cycles -= 8;
4029 for ( ; ; ) {
4030
4031 r += 2;
4032
4033 Z80_READ_BYTE(hl, x);
4034 Z80_OUTPUT_BYTE(C, x);
4035
4036 hl += d;
4037 if (--b)
4038
4039 elapsed_cycles += 21;
4040
4041 else {
4042
4043 f = Z80_Z_FLAG;
4044 elapsed_cycles += 16;
4045 break;
4046
4047 }
4048
4049 f = SZYX_FLAGS_TABLE[b];
4050 pc -= 2;
4051 break;
4052
4053 }
4054
4055 HL = hl;
4056 B = b;
4057
4058 f |= x >> (7 - Z80_N_FLAG_SHIFT);
4059 x += hl & 0xff;
4060 f |= x & 0x0100 ? HC_FLAGS : 0;
4061 f |= SZYXP_FLAGS_TABLE[(x & 0x07) ^ b]
4062 & Z80_P_FLAG;
4063 F = f;
4064
4065 break;
4066
4067 }
4068
4069 /* Prefix group. */
4070
4071 case CB_PREFIX: {
4072
4073 /* Special handling if the 0xcb prefix is
4074 * prefixed by a 0xdd or 0xfd prefix.
4075 */
4076
4077 if (registers != state.register_table) {
4078
4079 r--;
4080
4081 /* Indexed memory access routine will
4082 * correctly update pc.
4083 */
4084
4085 Z80_FETCH_BYTE(pc + 1, opcode);
4086
4087 } else {
4088
4089 Z80_FETCH_BYTE(pc, opcode);
4090 pc++;
4091
4092 }
4093 instruction = CB_INSTRUCTION_TABLE[opcode];
4094
4095 repeatLoop = true;
4096 break;
4097
4098 }
4099
4100 case DD_PREFIX: {
4101
4102 registers = state.dd_register_table;
4103
4104 Z80_FETCH_BYTE(pc, opcode);
4105 pc++;
4106 instruction = INSTRUCTION_TABLE[opcode];
4107 repeatLoop = true;
4108 break;
4109
4110 }
4111
4112 case FD_PREFIX: {
4113
4114 registers = state.fd_register_table;
4115
4116 Z80_FETCH_BYTE(pc, opcode);
4117 pc++;
4118 instruction = INSTRUCTION_TABLE[opcode];
4119 repeatLoop = true;
4120 break;
4121
4122 }
4123
4124 case ED_PREFIX: {
4125
4126 registers = state.register_table;
4127 Z80_FETCH_BYTE(pc, opcode);
4128 pc++;
4129 instruction = ED_INSTRUCTION_TABLE[opcode];
4130 repeatLoop = true;
4131 break;
4132
4133 }
4134
4135 /* Special/pseudo instruction group. */
4136
4137 case ED_UNDEFINED: {
4138
4139 #ifdef Z80_CATCH_ED_UNDEFINED
4140
4141 state.status = Z80_STATUS_FLAG_ED_UNDEFINED;
4142 pc -= 2;
4143
4144 #endif
4145
4146 break;
4147
4148 }
4149
4150 }
4151
4152 } while (repeatLoop);
4153
4154 state.r = (state.r & 0x80) | (r & 0x7f);
4155 state.pc = pc & 0xffff;
4156
4157 return elapsed_cycles;
4158}
4159
4160
4161}; // fabgl namespace
Z80.h
This file contains fabgl::Z80 definition.
B
uint8_t B
Definition: displaycontroller.h:2
Y
int16_t Y
Definition: displaycontroller.h:1
R
uint8_t R
Definition: displaycontroller.h:0