MCP23S17.h

Go to the documentation of this file.

/*
  Created by Fabrizio Di Vittorio (fdivitto2013@gmail.com) - <http://www.fabgl.com>
  Copyright (c) 2019-2022 Fabrizio Di Vittorio.
  All rights reserved.
 
 
* Please contact fdivitto2013@gmail.com if you need a commercial license.
 
 
* This library and related software is available under GPL v3.
 
  FabGL is free software: you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation, either version 3 of the License, or
  (at your option) any later version.
 
  FabGL is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.
 
  You should have received a copy of the GNU General Public License
  along with FabGL.  If not, see <http://www.gnu.org/licenses/>.
 */
 
 
 
#pragma once
 
 
 
#include "driver/spi_master.h"
 
#include "fabutils.h"
 
 
 
namespace fabgl {
 
 
 
#define MCP_SPI_FREQ  10000000   // it seems to work up to 23000000!! (but datasheet specifies 10000000)
#define MCP_DMACHANNEL       2
 
 
#define MCP_MAXDEVICES       2
 
 
#define MCP_PORTA            0
#define MCP_PORTB            1
 
 
#define MCP_A0               0
#define MCP_A1               1
#define MCP_A2               2
#define MCP_A3               3
#define MCP_A4               4
#define MCP_A5               5
#define MCP_A6               6
#define MCP_A7               7
 
#define MCP_B0               8
#define MCP_B1               9
#define MCP_B2              10
#define MCP_B3              11
#define MCP_B4              12
#define MCP_B5              13
#define MCP_B6              14
#define MCP_B7              15
 
 
// bank 0 registers (A = reg + 0, B = reg + 1)
#define MCP_IODIR         0x00
#define MCP_IPOL          0x02
#define MCP_GPINTEN       0x04
#define MCP_DEFVAL        0x06
#define MCP_INTCON        0x08
#define MCP_IOCON         0x0A
#define MCP_GPPU          0x0C
#define MCP_INTF          0x0E
#define MCP_INTCAP        0x10
#define MCP_GPIO          0x12
#define MCP_OLAT          0x14
 
 
// bank 1 registers (A = reg + 0, B = reg + 0x10)
#define MCP_BNK1_IODIR    0x00
#define MCP_BNK1_IPOL     0x01
#define MCP_BNK1_GPINTEN  0x02
#define MCP_BNK1_DEFVAL   0x03
#define MCP_BNK1_INTCON   0x04
#define MCP_BNK1_IOCON    0x05
#define MCP_BNK1_GPPU     0x06
#define MCP_BNK1_INTF     0x07
#define MCP_BNK1_INTCAP   0x08
#define MCP_BNK1_GPIO     0x09
#define MCP_BNK1_OLAT     0x0A
 
 
// IOCON bits
#define MCP_IOCON_BANK    0x80   // Controls how the registers are addressed (0 = bank0)
#define MCP_IOCON_MIRROR  0x40   // INT Pins Mirror bit (1 = mirrored)
#define MCP_IOCON_SEQOP   0x20   // Sequential Operation mode bit (1 = not increment)
#define MCP_IOCON_DISSLW  0x10   // Slew Rate control bit for SDA output (I2C only)
#define MCP_IOCON_HAEN    0x08   // Hardware Address Enable bit
#define MCP_IOCON_ODR     0x04   // Configures the INT pin as an open-drain output (1 = open-drain)
#define MCP_IOCON_INTPOL  0x02   // This bit sets the polarity of the INT output pin (1 = active-high)
 
 
#define MCP_GPIO2REG(basereg, gpio) ((basereg) + ((gpio) >> 3))
#define MCP_GPIO2MASK(gpio)         (1 << ((gpio) & 7))
 
 
enum class MCPDir {
  Input,    
  Output    
};
 
 
enum class MCPIntTrigger {
  DefaultChange,    
  PreviousChange    
};
 
 
class MCP23S17 {
 
public:
 
  MCP23S17();
  ~MCP23S17();
 
 
 
 
  bool begin(int MISO = -1, int MOSI = -1, int CLK = -1, int CS = -1, int CSActiveState = -1, int host = HSPI_HOST);
 
  void end();
 
  bool available()     { return m_SPIDevHandle != nullptr; }
 
  bool initDevice(uint8_t hwAddr);
 
 
 
 
  void writeReg(uint8_t addr, uint8_t value, uint8_t hwAddr = 0);
 
  uint8_t readReg(uint8_t addr, uint8_t hwAddr = 0);
 
  void writeReg16(uint8_t addr, uint16_t value, uint8_t hwAddr = 0);
 
  uint16_t readReg16(uint8_t addr, uint8_t hwAddr = 0);
 
 
 
 
  void enableINTMirroring(bool value, uint8_t hwAddr = 0);
 
  void enableINTOpenDrain(bool value, uint8_t hwAddr = 0);
 
  void setINTActiveHigh(bool value, uint8_t hwAddr = 0);
 
  bool getINTActiveHigh(uint8_t hwAddr = 0)                              { return readReg(MCP_IOCON, hwAddr) & MCP_IOCON_INTPOL; }
 
 
 
 
  void setPortDir(int port, uint8_t value, uint8_t hwAddr = 0)           { writeReg(MCP_IODIR + port, value, hwAddr); }
 
  uint8_t getPortDir(int port, uint8_t hwAddr = 0)                       { return readReg(MCP_IODIR + port, hwAddr); }
 
  void setPortInputPolarity(int port, uint8_t value, uint8_t hwAddr = 0) { writeReg(MCP_IPOL + port, value, hwAddr); }
 
  void enablePortPullUp(int port, uint8_t value, uint8_t hwAddr = 0)     { writeReg(MCP_GPPU + port, value, hwAddr); }
 
  uint8_t getPortPullUp(int port, uint8_t hwAddr = 0)                    { return readReg(MCP_GPPU + port, hwAddr); }
 
  void writePort(int port, uint8_t value, uint8_t hwAddr = 0)            { writeReg(MCP_OLAT + port, value, hwAddr); }
 
  uint8_t readPort(int port, uint8_t hwAddr = 0)                         { return readReg(MCP_GPIO + port, hwAddr); }
 
  void writePort16(uint16_t value, uint8_t hwAddr = 0)                   { writeReg16(MCP_OLAT, value, hwAddr); }
 
  uint16_t readPort16(uint8_t hwAddr = 0)                                { return readReg16(MCP_GPIO, hwAddr); }
 
 
 
 
  void configureGPIO(int gpio, MCPDir dir, bool pullup = false, uint8_t hwAddr = 0);
 
  void writeGPIO(int gpio, bool value, uint8_t hwAddr = 0);
 
  bool readGPIO(int gpio, uint8_t hwAddr = 0);
 
 
 
 
  void enableInterrupt(int gpio, MCPIntTrigger trigger, bool defaultValue = false, uint8_t hwAddr = 0);
 
  void disableInterrupt(int gpio, uint8_t hwAddr = 0);
 
 
 
 
  uint8_t getPortIntFlags(int port, uint8_t hwAddr = 0)                  { return readReg(MCP_INTF + port, hwAddr); }
 
  uint8_t getPortIntCaptured(int port, uint8_t hwAddr = 0)               { return readReg(MCP_INTCAP + port, hwAddr); }
 
 
 
 
  void writePort(int port, void const * buffer, size_t length, uint8_t hwAddr = 0);
 
  void readPort(int port, void * buffer, size_t length, uint8_t hwAddr = 0);
 
 
private:
 
  bool SPIBegin(int CSActiveState);
  void SPIEnd();
 
  gpio_num_t          m_MISO;
  gpio_num_t          m_MOSI;
  gpio_num_t          m_CLK;
  gpio_num_t          m_CS;
  spi_host_device_t   m_SPIHost;
 
  spi_device_handle_t m_SPIDevHandle;
 
  // cached registers
  uint8_t             m_IOCON[MCP_MAXDEVICES];
};
 
 
 
 
 
 
 
 
 
} // fabgl namespace